A.5.1. AXI master port

Table A.5 shows the AXI master port signals for the L2 interface. With the exception of the ACLKENMm, all signals are only sampled or driven on CLKIN edges when ACLKENMm is asserted, see AMBA interface clocking for more information.

Table A.5. AXI master port signals for the L2 interface

SignalDirectionDescription
ACLKENMmInput

Clock enable for the AXI master port.

Write address channel
 AWADDRMm[31:0]Output

Transfer start address.

 AWBURSTMm[1:0]Output

Write burst type.

 AWCACHEMm[3:0]Output

Provides decode information for outer attributes:

b0000 = Strongly Ordered.

b0001 = Device.

b0011 = Normal, Non-cacheable.

b0110 = Normal, Cacheable. write-through.

b1111 = Normal, Cacheable. write-back, write allocation.

b0111 = Normal, Cacheable. write-back, no write allocation.

Note

The AXI specification describes these encodings using the pre-ARMv6 terms such as cacheable-bufferable. These terms are equivalent to the ARMv6 memory-type descriptions such as Normal, Non-cacheable used here.

 AWIDMm[3:0]Output

The identification tag for the write address group of signals.

 AWLENMm[3:0]Output

Write transfer burst length.

 AWLOCKMm[1:0]Output

Lock signal.

 AWPROTMm[2:0]Output

Protection type.

 AWREADYMmInput

Address ready. The slave uses this signal to indicate that it can accept the address.

 AWSIZEMm[2:0]Output

Indicates the size of the transfer.

 AWINNERMm[3:0]Output

Provides inner attribute information for the write address channel. See Table 9.2 for information about the encoding of this signal.[a]

 AWSHAREMm[0]Output

Indicates the shareability of the address:

0 = non-shared

1 = shared.

 AWVALIDMmOutput

Indicates address and control are valid.

Write data channel
 WDATAMm[63:0]OutputWrite data.
 WIDMm[3:0]OutputThe identification tag for the write data group of signals.
 WLASTMmOutputIndicates the last data transfer of a burst.
 WREADYMmInputIndicates that the slave is ready to accept write data
 WSTRBMm[7:0]OutputWrite strobes used to indicate which byte lanes must be updated.
 WVALIDMmOutputIndicates address and control are valid.
Write response channel
 BIDMm[3:0]InputThe identification tag for the write response signal.
 BREADYMmOutputIndicates that the CPU is ready to accept write response.
 BRESPMm[1:0]Input

Write response.

 BVALIDMmInputIndicates that a valid write response is available.
Read address channel
 ARADDRMm[31:0]OutputInstruction fetch burst start address.
 ARBURSTMm[1:0]OutputBurst type.
 ARCACHEMm[3:0]Output

Provides decode information for outer attributes:

b0000 = Strongly Ordered.

b0001 = Device.

b0011 = Normal, Non-cacheable.

b0110 = Normal, Cacheable. write-through.

b1111 = Normal, Cacheable. write-back, write allocation.

b0111 = Normal, Cacheable. write-back, no write allocation.

Note

The AXI specification describes these encodings using the pre-ARMv6 terms such as cacheable-bufferable. These terms are equivalent to the ARMv6 memory-type descriptions such as Normal, Non-cacheable used here.

 ARIDMm[3:0]OutputIdentification tag for the read address group of signals
 ARLENMm[3:0]OutputInstruction fetch burst length.
 ARLOCKMm[1:0]OutputLock signal.
 ARPROTMm[2:0]OutputProtection type.
 ARREADYMmInputAddress ready. The slave uses this signal to indicate that it can accept the address.
 ARSIZEMm[2:0]OutputIndicates the size of the transfer.
 ARINNERMm[3:0]Output

Provides inner attribute for the read address channel. See Table 9.2 for information about the encoding of this signal.[a]

 ARSHAREMmOutput

Indicates the shareability of the address:

0 = non-shared

1 = shared.

 ARVALIDMmOutputIndicates address and control are valid.
Read Data Channel
 RDATAMm[63:0]InputRead Data.
 RIDMm[3:0]InputThe identification tag for the read data group of signals.
 RLASTMmInputIndicates the last transfer in a read burst.
 RREADYMmOutputRead ready signal indicating that the bus master can accept read data and response information.
 RRESPMm[1:0]InputRead response.
 RVALIDMmInputIndicates that read data is available.

[a] This is an AXI extension signal.


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