9.3.8. Normal write merging

A store instruction to Non-cacheable, or write-through Normal memory might not result in an AXI transfer because of the merging of store data in the internal buffers.

The STB can detect when it contains more than one write request to the same cache line for write-through Cacheable or Non-cacheable Normal memory. This means it can combine the data from more than one instruction into a single write burst to improve the efficiency of the AXI port. If the AXI master receives several write requests that do not form a single contiguous burst it can choose to output a single burst, with the WSTRBW signal low for the bytes that do not have any data.

For write accesses to Normal memory, the STB can perform writes out of order, if there are no address dependencies. It can do this to best use its ability to merge accesses.

The instruction sequence in Example 9.1 shows the merging of writes.

Example 9.1. Write merging

MOV r0, #0x4000
STRH  r1, [r0, #0x18]; Store a halfword at 0x4018
STR   r2, [r0, #0xC] ; Store a word at 0x400C
STMIA r0, {r4-r7}    ; Store four words at 0x4000
STRB  r3, [r0, #0x1D]; Store a byte at 0x401D

If the memory at address 0x4000 is marked as Strongly Ordered or Device type memory, the AXI transactions shown in Table 9.22 are generated.

Table 9.22. AXI transactions for Strongly Ordered or Device type memory

0x4018Incr16-bit1 data transfer0b00000011
0x400CIncr32-bit1 data transfer0b11110000
0x4000Incr32-bit4 data transfers





0x401DIncr8-bit1 data transfer0b00100000

In Example 9.1, each store instruction produces an AXI burst of the same size as the data written by the instruction.

Table 9.23 shows a possible resulting transaction if the same memory is marked as Non-cacheable Normal, or Cacheable write-through.

Table 9.23. AXI transactions for Non-cacheable Normal or Cacheable write-through memory

0x4000Incr64-bit4 data transfers





In this example:

The transactions shown in Table 9.23 show this behavior. They are provided as examples only, and are not an exhaustive description of the AXI transactions. Depending on the state of the processor, and the timing of the accesses, the actual bursts generated might have a different size and length to the examples shown, even for the same instruction.

If the same memory is marked as write-back Cacheable, and the addresses are allocated into a cache line, no AXI write transactions occur until the cache line is evicted and performs a write-back transaction. See Cache line write-back (eviction).

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