9.7. Peripheral interfaces

The processor has three peripheral interfaces. Accesses to the peripheral interfaces have lower latency, typically to half the latency of accesses to the AXI master interface. The port is used for:

The three peripheral interfaces use two physical ports, a 32-bit wide AXI master port that conforms to the AXI3 standard as described in the AMBA AXI Protocol Specification and an optional 32-bit wide AHB-Lite master port that conforms to the AHB-Lite standard as described in the AMBA AHB Protocol Specification.

The AXI peripheral port is sub-divided into:

The LLPP Virtual AXI is independent of the LLPP Normal AXI and the LLPP AHB peripheral interface from an ordering point of view. Accesses to both the AXI peripheral interfaces use the same physical AXI port but have different AXI IDs.

The AXI peripheral port has an address buffer and a data buffer, each of which has three entries. Each entry in the address buffer holds 32 bits of address, and an entry in the data buffer holds 32 bits of data. No merging is possible between the entries of a buffer. The LLPP Normal AXI and LLPP Virtual AXI share the address and data buffer.

The AHB peripheral port has its own address and data buffers. The address buffer has three entries and the data buffer has four entries. Each entry holds 32 bits. No merging is possible between the entries of a buffer.

The maximum number of outstanding write accesses that the processor posts onto the LLPP Virtual AXI is 3 and 15 for the LLPP Normal AXI.

AHB-Lite does not have the ability to do posted and out-of-order transactions, so the AHB peripheral port does not have a separate virtual interface.

Table 9.44 shows the AXI peripheral port attributes.

Table 9.44. AXI peripheral port attributes

Write issuing capability of LLPP Normal AXI1515 outstanding writes on (non-virtual) AXI peripheral interface
Write issuing capability of LLPP Virtual AXI33 outstanding writes on virtual AXI peripheral interface
Read issuing capability1-
Combined issuing capability19Maximum number of posted writes on all AXI peripheral interfaces and a read
Write ID capability2-
Write interleave capability1The AXI peripheral port presents all write data in order
Read ID capability2-

The peripheral ports can run at the same frequency as the processor or at a lower synchronous frequency. See AMBA interface clocking for more information.

In addition, the peripheral ports produce or check parity bits for each AXI or AHB channel. These additional signals are not part of the AXI or AHB specification, though some make use of AXI extension signals.

The following sections describe the attributes of the LLPP interfaces:

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