5.4. Controlling instruction prefetch and program flow prediction

In the Cortex-R5 processor, the Z-bit, bit [11] of the SCTLR, does not control the program flow prediction. The Z-bit is read-as-one, writes-ignored and instead a number of control bits in the Auxiliary Control Register control the program flow and prefetch features. To disable the program flow prediction, you must disable the return stack and set the branch prediction policy to always not-taken. See c1, Auxiliary Control Register.

The fetch rate predictor can be disabled by setting FRCDIC in the Auxiliary Control Register. When the predictor is disabled, the PFU fetches instructions at the fastest rate possible.

The dynamic branch predictor is controlled with the BP field in the Auxiliary Control Register. In normal operation the branch prediction is taken from the global history table. You can also force the prediction to be always taken, or always not-taken. When the prediction is forced to a fixed direction, the processor does not update the global history table, and the historic pattern of branches is frozen. You can also disable the loop prediction logic and the logic for preventing thrashing, by setting DEOLP and DBHE respectively.

You can disable the return stack by setting RSDIS in the Auxiliary Control Register. When disabled, pushes onto the stack caused by call instructions are disabled and the stack pointer is frozen.

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