9.3.6. Non-cacheable or write-through writes

Store instructions to Non-cacheable or write-through Normal memory generate AXI bursts that are not necessarily the same size or length as the instruction implies. The AXI master port asserts byte-lane-strobes, WSTRBMm[7:0], to ensure that only the bytes that were written by the instruction are updated.

The tables in this section give examples of the types of AXI transaction that might result from various store instructions, accessing various addresses in Non-cacheable Normal memory. They are provided as examples only, and are not an exhaustive description of the AXI transactions. Depending on the state of the processor, and the timing of the accesses, the actual bursts generated might have a different size and length to the examples shown, even for the same instruction.

In addition, write operations to Normal memory can be merged to create more complex AXI transactions. See Normal write merging for examples.

Table 9.16 shows possible values of AWADDRMm, AWBURSTMm, AWSIZEMm, and AWLENMm for an STRH to Normal memory.

Table 9.16. STRH to Cacheable write-through or Non-cacheable Normal memory

Address[2:0]AWADDRMmAWBURSTMmAWSIZEMmAWLENMm

WSTRBMm

0x0 (byte 0)0x00Incr32-bit1 data transferb00000011
0x1 (byte 1)0x00Incr32-bit1 data transferb00000110
0x2 (byte 2)0x02Incr64-bit1 data transferb00001100
0x3 (byte 3)0x03Incr32-bit2 data transfers

b00001000

b00010000

0x4 (byte 4)0x04Incr16-bit1 data transferb00110000
0x5 (byte 5)0x05Incr32-bit1 data transferb01100000
0x6 (byte 6)0x06Incr16-bit1 data transferb11000000
0x7 (byte 7)

0x07

Incr

8-bit

1 data transfer

b10000000

0x08

Incr

8-bit

1 data transfer

b00000001


Table 9.17 shows possible values of AWADDRMm, AWBURSTMm, AWSIZEMm, and AWLENMm for an STR or an STM that transfers one register, an STM1, to Normal memory through the AXI master port.

Table 9.17. STR or STM1 to Cacheable write-through or Non-cacheable Normal memory

Address[2:0]AWADDRMmAWBURSTMmAWSIZEMmAWLENMmWSTRBMm
0x0 (byte 0) (word 0)0x00Incr32-bit1 data transferb00001111
0x1 (byte 1)0x01Incr64-bit1 data transferb00011110
0x2 (byte 2)0x00Incr64-bit1 data transferb00111100
0x3 (byte 3)0x03Incr64-bit2 data transfers

b01111000

b00000000

0x4 (byte 4) (word 1)0x04Incr32-bit1 data transferb11110000
0x5 (byte 5)0x05Incr32-bit2 data transfers

b11100000

b00000001

0x6 (byte 6)

0x06

0x08

Incr

Incr

16-bit

16-bit

1 data transfer

1 data transfer

b11000000

b00000011

0x7 (byte 7)0x04Incr32-bit2 data transfers

b10000000

b00000111


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