Store instructions to Non-cacheable or write-through Normal memory generate AXI bursts that are not necessarily the same size or length as the instruction implies. The AXI master port asserts byte-lane-strobes, WSTRBMm[7:0], to ensure that only the bytes that were written by the instruction are updated.

The tables in this section give examples of the types of AXI transaction that might result from various store instructions, accessing various addresses in Non-cacheable Normal memory. They are provided as examples only, and are not an exhaustive description of the AXI transactions. Depending on the state of the processor, and the timing of the accesses, the actual bursts generated might have a different size and length to the examples shown, even for the same instruction.

In addition, write operations to Normal memory can be merged to create more complex AXI transactions. See Normal write merging for examples.

Table 9.16 shows possible values of AWADDRMm, AWBURSTMm, AWSIZEMm, and AWLENMm for an STRH to Normal memory.

Table 9.17 shows possible values of AWADDRMm, AWBURSTMm, AWSIZEMm, and AWLENMm for an STR or an STM that transfers one register, an STM1, to Normal memory through the AXI master port.