A.5.2. AXI master port error detection signals

Table A.6 shows the AXI master port error detection signals. these signals are only generated if the processor is configured to include AXI bus parity. See Configurable options for more information.

Table A.6. AXI master port error detection signals

ARADDRPTYMm[3:0]OutputParity bits for ARADDRMm[a]
ARCTLPTYMm[3:0]OutputParity bits for the rest of the read address channel[a]
ARRPTYMmInputParity bit for ARREADYMm
ARUSERPTYMmOutputParity bit for sideband signals[a]
ARVPTYMmOutputParity bit for ARVALIDMm
AWADDRPTYMm[3:0]OutputParity bits for AWADDRMm.[a]
AWCTLPTYMm[3:0]OutputParity bits for the rest of the write address channel[a]
AWRPTYMmInputParity bit for AWREADYMm
AWUSERPTYMmOutputParity bit for sideband signals[a]
AWVPTYMmOutputParity bit for AWVALIDMm
AXIMCORRmOutputCorrectable error detected on RDATAMm
AXIMFATALm[4:0]OutputFatal error detected on AXI master, per channel {R, AR, B, W, AW}
BCTLPTYMm[1:0]InputParity for buffered response channel[a]
BRPTYMmOutputParity bit for BREADYMm
BVPTYMmInputParity bit for BVALIDMm

Address of correctable error, doubleword

RCTLPTYMm[1:0]InputParity for rest of read data channel[a]
RERRCODEMm[7:0]InputECC code for RDATAMm[a]
RRPTYMmOutputParity bit for RREADYMm
RVPTYMmInputParity bit for RVALIDMm
WCTLPTYMm[2:0]OutputParity bits for the rest of the write data channel[a]
WERRCODEMm[7:0]OutputECC code for WDATAMm[a]
WRPTYMmInputParity bit for WREADYMm
WVPTYMmInputParity bit for WVALIDMm

[a] This is an AXI extension signal.

[b] This address bus is also used by other AMBA masters: PPX and PPH.

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