A.5.5. ACP slave port

Table A.9 shows the ACP slave port signals.

Table A.9. ACP slave port signals

ACLKENCInputClock enable, shared between ACP slave and master port.
Write Address Channel  
 AWIDCS[1:0]InputThe identification tag for the write address group of signals.
 AWADDRCS[31:0]InputTransfer start address.
 AWLENCS[3:0]InputWrite transfer burst length.
 AWSIZECS[2:0]InputIndicates the size of the transfer.
 AWBURSTCS[1:0]InputWrite burst type.
 AWLOCKCS[1:0]InputLock signal.

Provides decode information for outer attributes:

b0000 = Strongly Ordered.

b0001 = Device.

b0011 = Normal, Non-cacheable.

b0110 = Normal, Cacheable. write-through.

b1111 = Normal, Cacheable. write-back, write allocation.

b0111 = Normal, Cacheable. write-back, no write allocation.


The AXI specification describes these encodings using the pre-ARMv6 terms such as cacheable-bufferable. These terms are equivalent to the ARMv6 memory-type descriptions such as Normal, Non-cacheable used here.

 AWPROTCS[2:0]InputProtection signals provide additional information about a bus access.
 AWCOHERENTCSInputRequire caches to be made coherent with this access.[a]
 AWUSERCS[3:0]InputFor transmission of other sideband information.[a]
 AWVALIDCSInputIndicates address and control are valid.
 AWREADYCSOutputAddress ready. The slave uses this signal to indicate it is ready to accept the address.
Write Response Channel  
 BIDCS[1:0]OutputThe identification tag for the write response signal.
 BRESPCS[1:0]OutputWrite response.
 BVALIDCSOutputIndicates that a valid write response is available.
 BREADYCSInputIndicates that the CPU is ready to accept write response.
 BMISSCS[1:0]OutputAccess did not hit in either cache, or coherency not required. One bit for each CPU.[a]
 BHITDIRTYCS[1:0]OutputAccess hit a dirty line, or Dormant CPU, and was not invalidated. One bit for each CPU.[a]
 BUSERCS[3:0]OutputFor transmission of other sideband information.[a]

[a] This is an AXI extension signal.

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