A.5.8. ACP master port error detection signals

Table A.12 shows the ACP master port error detection signals. These signals are only generated if the processor is configured to include AXI bus parity. See Configurable options for more information.

Table A.12. ACP master port error detection signals

SignalDirectionDescription
AWVPTYCMOutputParity bit for AWVALIDCM
AWRPTYCMInputParity bit for AWREADYCM
AWADDRPTYCM[3:0]OutputParity bits for AWADDRCM[a]
AWCTLPTYCM[3:0]OutputParity bits for the rest of the write address channel[a]
AWUSERPTYCMOutputParity bit for sideband signals[a]
BVPTYCMInputParity bit for BVALIDCM
BRPTYCMOutputParity bit for BREADYCM
BCTLPTYCM[1:0]InputParity for buffered response signal[a]
BUSERPTYCMInputParity bit for sideband signals[a]
ACPMFATAL[1:0]OutputFatal error, per channel, {B,AW}

[a] This is an AXI extension signal.


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