A.5.4. AXI slave port error detection signals

Table A.8 shows the AXI slave port error detection signals. These signals are only generated if the processor is configured to include AXI bus parity. See Configurable options for more information.

Table A.8. AXI slave port error detection signals

SignalDirectionDescription
ARADDRPTYSm[3:0]InputParity bits for ARADDRSm[a]
ARCTLPTYSm[3:0]InputParity bits for the rest of the read address channel[a]
ARRPTYSmOutputParity bit for ARREADYSm
ARUSERPTYSmInputParity bit for sideband signals[a]
ARVPTYSmInputParity bit for ARVALIDSm
AWADDRPTYSm[3:0]InputParity bits for AWADDRSm[a]
AWCTLPTYSm[3:0]InputParity bits for the rest of the write address channel[a]
AWRPTYSmOutputParty bit for AWREADYSm
AWUSERPTYSmInputParity bit for sideband signals[a]
AWVPTYSmInputParity bit for AWVALIDSm
AXISCORRmOutputCorrectable error, write data channel
AXISFATALm[4:0]OutputFatal error, per channel.
BCTLPTYSm[1:0]OutputParity for buffered response channel[a]
BRPTYSmOutputParity bit for BREADYSm
BVPTYSmInputParity bit for BVALIDSm
RCTLPTYSm[1:0]OutputParity for rest of read data channel[a]
RERRCODESm[7:0]InputECC code for RDATASm[a]
RRPTYSmOutputParity bit for RREADYSm
RVPTYSmOutputParity bit for RVALIDSm
SERRADDRm[22:3]OutputAddress of correctable error, within doubleword
SERRCSELm[3:0]OutputChip-select of correctable error.
WCTLPTYSm[2:0]InputParity bits for rest of write data channel[a]
WERRCODESm[7:0]InputECC code for WDATAMm[a]
WRPTYSmOutputParity bit for WREADYSm
WVPTYSmInputParity bit for WVALIDSm

[a] This is an AXI extension signal.


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