9.7.3. Peripheral interface attributes and permissions

Accesses to the peripheral interfaces from the LSU are checked against the MPU for access permission. Memory access attributes are exported on this interface. Access permissions for peripheral interface accesses are the same as the permission attributes that the MPU assigns to the same address. Instructions cannot be fetched from any of the peripheral interfaces, and therefore they behave as if they have the eXecute Never (XN) attribute, regardless of the MPU XN attribute. All instruction fetches from the peripheral interfaces generate a permission fault. See Chapter 7 Memory Protection Unit for more information about memory attributes, types, and permissions.

Note

If a peripheral interface region overlaps with a TCM region then the TCM region gets more priority and the overlapping memory gets the attributes of the TCM region.

The L1 memory system cannot cache any peripheral interface access even if the access is to Normal memory with a Cacheable attribute. Load or store multiple instructions accessing the peripheral port are not performed as long bursts, and are not interruptible-restartable, even when they are in Normal memory. ARM recommends that you do not perform multiples to the peripheral interface regardless of the memory type, because this might impact the interrupt latency.

Any unaligned access to Device or Strongly Ordered memory generates an alignment fault and therefore does not cause any peripheral interface access. This means that the access examples given in this chapter never show unaligned accesses to Device or Strongly Ordered memory.

Also any shared exclusive double to the AXI peripheral port or any shared exclusive to the AHB peripheral port generates an abort and therefore does not cause an access.

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