A.5.9. AXI peripheral port

Table A.13 shows the AXI peripheral port signals.

Table A.13. AXI peripheral port signals

SignalDirectionDescription
ACLKENPmInputClock enable for the AXI peripheral port.
Write Address Channel  
 AWIDPm[3:0]OutputThe identification tag for the write address group of signals.
 AWADDRPm[31:0]OutputTransfer start address.
 AWLENPm[3:0]OutputWrite transfer burst length.
 AWSIZEPm[2:0]OutputIndicates the size of the transfer.
 AWBURSTPm[1:0]OutputWrite burst type.
 AWLOCKPm[1:0]OutputLock signal.
 AWCACHEPm[3:0]Output

Provides decode information for outer attributes:

b0000 = Strongly Ordered.

b0001 = Device.

b0011 = Normal, Non-cacheable.

b0110 = Normal, Cacheable. write-through.

b1111 = Normal, Cacheable. write-back, write allocation.

b0111 = Normal, Cacheable. write-back, no write allocation.

Note

The AXI specification describes these encodings using the pre-ARMv6 terms such as cacheable-bufferable. These terms are equivalent to the ARMv6 memory-type descriptions such as Normal, Non-cacheable used here.

 AWPROTPm[2:0]OutputProtection type.
 AWVALIDPmOutputIndicates address and control are valid.
 AWREADYPmInputAddress ready. The slave uses this signal to indicate it is ready to accept the address.
Write Data Channel  
 WIDPm[3:0]OutputThe identification tag for the write data group of signals.
 WDATAPm[31:0]OutputWrite data.
 WSTRBPm[3:0]OutputWrite strobes used to indicate which byte lanes must be updated.
 WLASTPmOutputIndicates the last data transfer of a burst.
 WVALIDPmOutputIndicates address and control are valid.
 WREADYPmInputIndicates that the slave is ready to accept write data.
Write Response Channel  
 BIDPm[3:0]InputThe identification tag for the write response channel.
 BRESPPm[1:0]InputWrite response.
 BVALIDPmInputIndicates that a valid write response is available.
 BVPTYPmInputParity bit for BVALIDPm
 BREADYPm OutputIndicates that the CPU is ready to accept a write response.
 BRPTYPmOutputParity bit for BREADYPm
 BCTLPTYPm[1:0]InputParity for buffered response channel
Read Address Channel  
 ARIDPm[3:0]OutputIdentification tag for the read address group of signals.
 ARADDRPm[31:0]OutputInstruction fetch burst start address.
 ARLENPm[3:0]OutputInstruction fetch burst length.
 ARSIZEPm[2:0]OutputIndicates the size of the transfer.
 ARBURSTPm[1:0]OutputBurst type.
 ARLOCKPm[1:0]OutputLock signal.
 ARCACHEPm[3:0]Output

Provides decode information for outer attributes:

b0000 = Strongly Ordered.

b0001 = Device.

b0011 = Normal, Non-cacheable.

b0110 = Normal, Cacheable. write-through.

b1111 = Normal, Cacheable. write-back, write allocation.

b0111 = Normal, Cacheable. write-back, no write allocation.

Note

The AXI specification describes these encodings using the pre-ARMv6 terms such as cacheable-bufferable. These terms are equivalent to the ARMv6 memory-type descriptions such as Normal, Non-cacheable used here.

 ARPROTPm[2:0]OutputProtection type.
 ARVALIDPmOutputIndicates address and control are valid.
 ARREADYPmInputAddress ready. The slave uses this signal to indicate it is ready to accept the address.
Read Data Channel  
 RIDPm[3:0]InputThe identification tag for the read data group of signals.
 RDATAPm[31:0]InputRead data.
 RRESPPm[1:0]InputRead response.
 RLASTPmInputIndicates the last transfer in a read burst.
 RVALIDPmInputIndicates that read data is available.
 RREADYPmOutputRead ready signal indicating that the bus master can accept read data and response information.

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