D.2. Virtual AXI peripheral interface

Each Cortex-R5 CPU can perform memory transactions using the AXI master interface, the AXI peripheral interface or, if included, the AHB peripheral interface. Each of these interfaces is treated independently from an ordering point of view. The virtual AXI peripheral interface provides an additional interface that, although it shares the same physical port as the AXI peripheral interface, is treated independently from an ordering point of view.

The two AXI peripheral interfaces use different AXI IDs to enable the memory system to return responses out of order. They also have different limits on the number of outstanding writes permitted so, by selecting a particular interface for a peripheral, you can have some control over the maximum latency of accesses to that peripheral. If your AXI peripheral port memory system accepts outstanding write transactions, ARM recommends that you configure the peripheral interfaces so that the most latency critical peripheral, possibly an interrupt controller, is on the virtual AXI peripheral interface and all others elsewhere.

Note

  • The AXI peripheral interface and virtual AXI peripheral interface share write buffer logic, and write data is drained in order from this buffer. The interfaces use different IDs, so write responses can be received out-of-order. If the buffer contains writes to both interfaces, and the AXI peripheral interface writes are older, a virtual AXI peripheral interface read cannot start until the virtual AXI peripheral interface writes have all completed, and this in turn requires that the AXI peripheral interface writes have posted address and data to the bus though not necessarily completed.

  • Similarly, if the memory system on the AXI peripheral port returns all write responses in order, regardless of ID, this can force reads on one interface to wait for writes on a different interface. The same effect is possible if two CPU ports connect to a common memory bus that forces ordering.

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