2.3.1. Resets

Each Cortex-R5 CPU has the following inputs:


Main CPU reset. Resets the non-debug CPU logic.


CPU debug reset. Resets core-domain debug logic. This includes breakpoints, watchpoints and the DCC registers.


CPU debug reset. Resets debug-domain debug logic and the APB interface of the CPU.


  • For more information about the split between core-domain and debug-domain logic, see the ARM Architecture Reference Manual.

  • Cortex-R5 implements separate core and debug domains with the minimal architected set of debug domain registers.

The Cortex-R5 processor group, containing one or two CPUs, has the following resets:


ACP reset. Resets the ACP logic and both the ACP slave and master AXI interfaces.


Power-on reset. Resets the entire processor group including all implemented CPUs, debug logic and ACP. See Effects of resets on debug registers.

The following input is related to the reset functionality:


This signal, when asserted, stops the CPU from fetching instructions out of reset.

All these signals are active-LOW and are suitably synchronized within the processor. You must take care when generating these reset signals, for example, to ensure that they are glitch-free.

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