3.8.3. Interrupts

The processor has two interrupt inputs, for normal interrupts (nIRQm) and fast interrupts (nFIQm). Each interrupt pin, when asserted and not masked, causes the processor to take the appropriate type of interrupt exception. See Exceptions for more information. The CPSR.F and CPSR.I bits control masking of fast and normal interrupts respectively.

A number of features exist to improve the interrupt latency, that is, the time taken between the assertion of the interrupt input and the execution of the interrupt handler. By default, the processor uses the Low Interrupt Latency (LIL) behaviors introduced in version 6 and later of the ARM architecture. The processor also has a port for connection of a Vectored Interrupt Controller (VIC), and supports Non-Maskable Fast Interrupts (NMFI).

The following subsections describe interrupts:

Interrupt request

The IRQ exception is a normal interrupt caused by a LOW level on the nIRQm input. An IRQ has a lower priority than an FIQ, and is masked on entry to an FIQ sequence. You must ensure that the nIRQm input is held LOW until the processor acknowledges the interrupt request, either from the VIC interface or the software handler.

Irrespective of whether the exception is taken from ARM state or Thumb state, an IRQ handler returns from the interrupt by executing:

SUBS PC, R14_irq, #4

You can disable IRQ exceptions within a Privileged mode by setting the CPSR.I bit to b1. See Program status registers. IRQ interrupts are automatically disabled when an IRQ occurs, by setting the CPSR.I bit. You can use nested interrupts but it is up to you to save any corruptible registers and to re-enable IRQs by clearing the CPSR.I bit.

Fast interrupt request

The Fast Interrupt Request (FIQ) reduces the execution time of the exception handler relative to a normal interrupt. FIQ mode has eight private registers to reduce, or even remove the requirement for register saving (minimizing the overhead of context switching).

An FIQ is externally generated by taking the nFIQm input signal LOW. You must ensure that the nFIQm input is held LOW until the processor acknowledges the interrupt request from the software handler.

Irrespective of whether exception entry is from ARM state or Thumb state, an FIQ handler returns from the interrupt by executing:

SUBS PC, R14_fiq, #4

If Non-Maskable Fast Interrupts (NMFIs) are not enabled, you can mask FIQ exceptions by setting the CPSR.F bit to b1. For more information see:

FIQ and IRQ interrupts are automatically masked by setting the CPSR.F and CPSR.I bits when an FIQ occurs. You can use nested interrupts but it is up to you to save any corruptible registers and to re-enable interrupts.

Non-maskable fast interrupts

When NMFI behavior is enabled, FIQ interrupts cannot be masked by software. Enabling NMFI behavior ensures that when the FIQ mask, that is, the CPSR.F bit, has been cleared by the reset handler, fast interrupts are always taken as quickly as possible, except during handling of a fast interrupt. This makes the fast interrupt suitable for signaling critical events. NMFI behavior is controlled by a configuration input signal CFGNMFIm, that is asserted HIGH to enable NMFI operation. There is no software control of NMFI.

Software can detect whether NMFI operation is enabled by reading the NMFI bit of the SCTLR:

NMFI == 0

Software can mask FIQs by setting the CPSR.F bit to b1.

NMFI == 1

Software cannot mask FIQs.

For more information see c1, System Control Register.

When the NMFI bit in the SCTLR is b1:

  • an instruction writing b0 to the CPSR.F bit clears it to b0

  • an instruction writing b1 to the CPSR.F bit leaves it unchanged

  • the CPSR.F bit can be set to b1 only by an FIQ or reset exception entry.

Low interrupt latency

Low Interrupt Latency (LIL) is a set of behaviors that reduce the interrupt latency for the processor, and is enabled by default. That is, the FI bit [21] in the SCTLR is Read-as-One.

LIL behavior enables accesses to Normal memory, including multiword accesses and external accesses, to be abandoned part-way through execution so that the processor can react to a pending interrupt faster than would otherwise be the case. When an instruction is abandoned in this way, the processor behaves as if the instruction was not executed at all. If, after handling the interrupt, the interrupt handler returns to the program in the normal way using instruction SUBS pc, r14, #4, the abandoned instruction is re-executed. This means that some of the memory accesses generated by the instruction are performed twice.

Memory that is marked as Strongly Ordered or Device type is typically sensitive to the number of reads or writes performed. Because of this, instructions that access Strongly Ordered or Device memory are never abandoned when they have started accessing memory. These instructions always complete either all or none of their memory accesses. The same is true of all accesses to the AXI peripheral port, regardless of the memory type. Therefore, to minimize the interrupt latency, you must avoid the use of multiword load/store instructions to memory locations that are marked as Strongly Ordered or Device or are in the AXI or virtual AXI peripheral interface.

Interrupt controller

The processor includes a VIC port for connection of a Vectored Interrupt Controller (VIC). An interrupt controller is a peripheral that handles multiple interrupt sources. Features usually found in an interrupt controller are:

  • multiple interrupt request inputs, one for each interrupt source, and one or more amalgamated interrupt request outputs to the processor

  • the ability to mask out particular interrupt requests

  • prioritization of interrupt sources for interrupt nesting.

In a system with an interrupt controller with these features, software is still required to:

  • determine from the interrupt controller which interrupt source is requesting service

  • determine where the service routine for that interrupt source is loaded

  • mask or clear that interrupt source, before re-enabling processor interrupts to permit another interrupt to be taken.

A VIC does all these in hardware to reduce the interrupt latency. It supplies the starting address of the service routine corresponding to the highest priority asserted interrupt source directly to the processor. When the processor has accepted this address, it masks the interrupt so that the processor can re-enable interrupts without clearing the source. The PL192 VIC is an Advanced Microcontroller Bus Architecture (AMBA) compliant, System-on-Chip (SoC) peripheral that is developed, tested, and licensed by ARM.

You can use the VIC port to connect a PL192 VIC to the processor. See the ARM PrimeCell Vectored Interrupt Controller (PL192) Technical Reference Manual for more information about the PL192 VIC. You can enable the VIC port by setting the VE bit in the SCTLR. When the VIC port is enabled and an IRQ occurs, the processor performs an handshake over the VIC interface to obtain the address of the handling routine for the IRQ.

Interrupt entry flowchart

Figure 3.5 is a flowchart for processor interrupt recognition. It shows all the necessary decisions and actions for a complete interrupt entry.

Figure 3.5. Interrupt entry sequence

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For information on the I and F bits that Figure 3.5 shows, see Program status registers. For information on the V and VE bits that Figure 3.5 shows, see c1, System Control Register.

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