2.3.3. Clocking

The processor has a single clock input, CLKIN, that is used for the CPU or both CPUs in a twin-CPU configuration. The same clock is used for the ACP ports and logic, and the debug-APB interfaces.

The clock can be stopped indefinitely without loss of state.

The additional clock input, CLKIN2, is related to the dual-redundant core functionality, if included. If you are integrating a Cortex-R5 processor with dual-redundant core, contact the implementer of that macrocell for information about how to connect the clock inputs.

This section describes:

AMBA interface clocking

The AXI master, AXI slave, ACP, debug-APB, and AXI and AHB peripheral ports must be connected to the AMBA systems that are synchronous to the processor clock, CLKIN, even if this might be at a lower frequency. This means that every rising edge on the AMBA system clock must be synchronous to a rising edge on CLKIN.

The AXI master interface clock enable signal ACLKENMm, the AXI slave interface clock enable signal ACLKENSm, ACP clock enable ACLKENC, debug-APB block enable PCLKENDBGm, and AHB and AXI peripheral port clock enables ACLKENP and HCLKENP respectively must be asserted on every CLKIN rising edge for which there is a simultaneous rising edge on the AXI system clock.

Figure 2.5 shows an example in which the processor is clocked at 400MHz (CLKIN), while the AXI system connected to the AXI master interface is clocked at 200MHz (ACLKM). The ACLKENMm clock indicates the relationship between the two clocks.

Figure 2.5. AXI interface clocking

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If the AMBA system connected to an interface is clocked at the same frequency as the processor, then the corresponding clock enable signal must be tied HIGH.

Clock gating

In Standby Mode the CPU can gate its own clock to save power. See Chapter 10 Power Control for more information about Standby Mode. You can use the nCLKSTOPPEDm output to gate the clock to the TCMs when the CPU is gating its own clock in Standby mode. If you do, you must design the logic so that the TCM clock starts running within three cycles of nCLKSTOPPEDm going HIGH.

Figure 2.6 shows an example of an ATCM access occurring immediately after CPU0 exits Standby Mode. nCLKSTOPPED0 indicates when the CPU internal clock, shown as CPU_CLK0, has been restarted. The clock to the ATCM, shown as ATCM_CLK0, has been gated off in Standby Mode and is restarted by the third cycle in order to permit the ATCM to respond to the access that CPU0 presents by asserting ATCEN00. This example shows the worst-case, that is, the earliest TCM access that the CPU can generate after exiting Standby Mode.

Figure 2.6. Standby, wake-up

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