4.3.34. Peripheral interface region registers

There are three peripheral interface region registers, one for each of the:

The Peripheral Interface Region Register characteristics are:

Purpose

Describe the size and base of the interface, and contain an enable bit for the interface

Usage constraints

The Peripheral Interface Region Registers are:

  • Read/write registers.

  • Accessible in Privileged mode only.

  • The enable bits for the LLPP Normal AXI and AHB peripheral interface region registers are initialized immediately after reset, from the values on the INITPPXm and INITPPHm pins.

  • The LLPP Virtual AXI region register enable resets to zero.

Configurations

Available in all processor configurations.

Attributes

Figure 4.58 shows the Peripheral Interface Region Register bit assignments.

Figure 4.58. Peripheral Interface Region Register bit assignments

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Table 4.61 shows the Peripheral Interface Region Register bit assignments.

Table 4.61. Peripheral Interface Region Register bit assignments

BitNameTypeFunction
[31:12]BaseAddressRO

The base address of the interface, given as bits [31:12] of the address of the interface in the memory map. This value is configured during integration.

[11:7]-ROReserved.
[6:2]SizeRO

Returns the size of the interface configured during integration:

0b00000 = no PP present

0b00011 = 4KB

...

0b10111 = 4GB

[1]-ROReserved.
[0]EnRW

Interface enable bit:

0 = Disabled

1 = Enabled. The reset value of this bit is:

  • for LLPP Normal AXI, determined by INITPPXm

  • for LLPP Virtual AXI, always 0

  • for AHB peripheral interface, determined by INITPPHm.


To access the Peripheral Interface Region Registers, read CP15 with:

MRC p15, 0, <Rt>, c15, c0, 1; Read LLPP Normal AXI region register
MRC p15, 0, <Rt>, c15, c0, 2; Read LLPP Virtual AXI region register
MRC p15, 0, <Rt>, c15, c0, 3; Read AHB peripheral interface region register
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