4.3.20. Fault Status and Address Registers

The processor reports the status and address of faults that occur during its operation. For both data and instruction faults there are two Fault Status Registers (FSRs) and one Fault Address Register (FAR).

Fields within the Data and Instruction FSRs indicate the priority and source of a fault and the validity of the address in the corresponding FAR. Table 4.28 shows this encoding for the FSRs.

Table 4.28. Fault Status Register encodings

PrioritySources

FSR [10,3:0]

FAR
HighestAlignment0b00001Valid
Background0b00000Valid
Permission0b01101Valid
Synchronous External Abort0b01000Valid
Asynchronous External Abort0b10110Unpredictable
Synchronous Parity or ECC Error 0b11001Valid
Asynchronous Parity or ECC Error 0b11000Unpredictable
LowestDebug Event0b00010Unchanged

All other encodings for these FSR bits are Reserved.

c5, Data Fault Status Register

The DFSR is:

  • a read/write register

  • accessible in Privileged mode only.

The DFSR characteristics are:

Purpose

Holds status information regarding the source of the last data abort.

Usage constraints

The DFSR is:

  • a read/write register

  • accessible in Privileged mode only.

Configurations

Available in all processor configurations.

Attributes

Figure 4.31 shows the DFSR bit assignments.

Figure 4.31. DFSR bit assignments

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Table 4.29 shows the DFSR bit assignments.

Table 4.29. DFSR bit assignments

Bits

NameFunction

[31:13]

-SBZ.

[12]

SD

Distinguishes between an AXI Decode or Slave error on an external abort. This bit is only valid for external aborts. For all other aborts types of abort, this bit is set to zero:

0 = AXI Decode error (DECERR), or AHB error, caused the abort

1 = AXI Slave error (SLVERR), or unsupported exclusive access, for example exclusive access using the AHB peripheral port, caused the abort.

[11]

RW

Indicates whether a read or write access caused an abort:

0 = read access caused the abort

1 = write access caused the abort.

[10][a]

S

Part of the Status field.

[9:8]

-

Always read as 0. Writes ignored.

[7:4]

DomainSBZ. This is because domains are not implemented in this processor.

[3:0][a]

Status

Indicates the type of fault generated. To determine the data fault, you must use bit [12] and bit [10] in conjunction with bits [3:0].

[a] For more information on how these bits are used in reporting faults, see Table 4.28.


To use the DFSR read or write CP15 with:

MRC p15, 0, <Rd>, c5, c0, 0  ; Read DFSR
MCR p15, 0, <Rd>, c5, c0, 0  ; Write DFSR

c5, Instruction Fault Status Register

The IFSR characteristics are:

Purpose

Holds status information regarding the source of the last instruction abort.

Usage constraints

The IFSR is:

  • a read/write register

  • accessible in Privileged mode only.

Configurations

Available in all processor configurations.

Attributes

Figure 4.32 shows the IFSR bit assignments.

Figure 4.32. IFSR bit assignments

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Table 4.30 shows the IFSR bit assignments.

Table 4.30. IFSR bit assignments

BitsNameFunction
[31:13]-SBZ.
[12]SD

Distinguishes between an AXI Decode or Slave error on an external abort. This bit is only valid for external aborts. For all other aborts types of abort, this bit is set to zero:

0 = AXI Decode error (DECERR) caused the abort

1 = AXI Slave error (SLVERR) caused the abort.

[11]-SBZ.
[10][a]S

Part of the Status field.

[9:8]-SBZ.
[7:4]DomainSBZ. This is because domains are not implemented in this processor.
[3:0][a]Status

Indicates the type of fault generated. To determine the instruction fault, bit [12] and bit [10] must be used in conjunction with bits [3:0].

[a] For more information on how these bits are used in reporting faults, see Table 4.28.


To access the IFSR read or write CP15 with:

MRC p15, 0, <Rd>, c5, c0, 1  ; Read IFSR
MCR p15, 0, <Rd>, c5, c0, 1  ; Write IFSR

c5, Auxiliary Fault Status Registers

There are two auxiliary fault status registers:

  • the Auxiliary Data Fault Status Register (ADFSR)

  • the Auxiliary Instruction Fault Status Register (AIFSR).

The auxiliary fault status registers characteristics are:

Purpose

Provide additional information about data and instruction parity, ECC, and external TCM errors.

Usage constraints

The auxiliary fault status registers are:

  • Read/write registers.

  • Accessible in Privileged mode only.

  • The contents of an auxiliary fault status register are only valid when the corresponding Data or Instruction Fault Status Register indicates that a parity or ECC error has occurred. At other times the contents of the auxiliary fault status registers are Unpredictable.

Configurations

Available in all processor configurations.

Attributes

Figure 4.33 shows the auxiliary fault status registers bit assignments.

Figure 4.33. Auxiliary fault status registers bit assignments

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Table 4.31 shows the auxiliary fault status registers bit assignments.

Table 4.31. ADFSR and AIFSR bit assignments

BitsNameFunction
[31:28]-SBZ.
[27:24]CacheWay[a]

The value returned in this field indicates the cache way or ways in which the error occurred.

[23:22]Side

The value returned in this field indicates the source of the error. See Table 4.32 for the encodings.

[21]Recoverable error

The value returned in this field indicates if the error is recoverable.

0 = Unrecoverable error.

1 = Recoverable error. This includes all correctable parity/ECC errors and recoverable TCM external errors.

[20]SideExt

The value returned in this field indicates the source of the error. See Table 4.32 for the encodings.

[19:14]-SBZ.
[13:5]Index[b]

This field returns the index value for the access giving the error.

[4:0]-SBZ.

[a] This field is only valid for data cache store parity/ECC errors, otherwise it is Unpredictable.

[b] This field is only valid for data cache store parity/ECC errors. On the AIFSR, and for TCM accesses, this field SBZ.


Table 4.32 shows the encodings for the SideExt and Side bits.

Table 4.32. SideExt and Side bit encodings

Bit valuesMeaning
SideExtSide
000Cache/AXIM
001ATCM
010BTCM
011Reserved
100
101AXI peripheral port, including virtual interface
110AHB peripheral port
111Reserved

To access the auxiliary fault status registers, read or write CP15 with:

MRC p15, 0, <Rd>, c5, c1, 0  ; Read Auxiliary Data Fault Status Register 
MCR p15, 0, <Rd>, c5, c1, 0  ; Write Auxiliary Data Fault Status Register 
MRC p15, 0, <Rd>, c5, c1, 1  ; Read Auxiliary Instruction Fault Status Register
MCR p15, 0, <Rd>, c5, c1, 1  ; Write Auxiliary Instruction Fault Status Register

c6, Data Fault Address Register

The DFAR characteristics are:

Purpose

Holds the address of the fault when a synchronous abort occurs.

Usage constraints

The DFAR is:

  • a read/write register

  • accessible in Privileged mode only.

Configurations

Available in all processor configurations.

Attributes

The DFAR bits [31:0] contain the address where the synchronous abort occurred.

To access the DFAR read or write CP15 with:

MRC p15, 0, <Rd>, c6, c0, 0 ; Read DFAR
MCR p15, 0, <Rd>, c6, c0, 0 ; Write DFAR

A write to this register sets the DFAR to the value of the data written. This is useful for a debugger to restore the value of the DFAR.

The processor also updates the DFAR on debug exception entry because of watchpoints. See Effect of debug exceptions on CP15 registers and DBGWFAR for more information.

c6, Instruction Fault Address Register

The IFAR characteristics are:

Purpose

Holds the address of the instruction that caused a prefetch abort.

Usage constraints

The IFAR is:

  • a read/write register

  • accessible in Privileged mode only.

Configurations

Available in all processor configurations.

Attributes

The IFAR bits [31:0] contain the Instruction Fault address.

To access the IFAR read or write CP15 with:

MRC p15, 0, <Rd>, c6, c0, 2 ; Read IFAR
MCR p15, 0, <Rd>, c6, c0, 2 ; Write IFAR

A write to this register sets the IFAR to the value of the data written. This is useful for a debugger to restore the value of the IFAR.

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