4.3.32. Build Options Registers

Note

In a twin-CPU system, some options can be configured independently for each CPU. For these options, the Options Register reflects the options for the CPU containing the register. Other options are shared, and the options register contains the same value for both CPUs.

c15, Build Options 1 Register

The Build Options 1 Register characteristics are:

Purpose

Reflects the build configuration options used to build the processor.

Usage constraints

The Build Options 1 Register is:

  • a read-only register

  • accessible in Privileged mode only

  • pin-configuration options are shown in a separate register, see Pin Options Register.

Configurations

Available in all processor configurations.

Attributes

Figure 4.55 shows the Build Options 1 Register bit assignments.

Figure 4.55. Build Options 1 Register bit assignments

To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.


Table 4.58 shows the Build Options 1 Register bit assignments.

Table 4.58. Build Options 1 Register bit assignments

BitsNameFunction
[31:12]TCM_HI_INIT_ADDRDefault high address for the TCM.
[11:2]-SBZ.
[1]FLOAT_PRECISION

Indicates whether double-precision floating point is implemented:

0 = Double-precision FP implemented, or no FPU implemented

1 = No double-precision FP implemented.

[0]PP_BUS_ECC

Indicates whether the peripheral ports were built with bus-ECC:

0 = bus-ECC not included on peripheral ports

1 = bus-ECC included on peripheral ports.


To access the Build Options 1 Register, read CP15 with:

MRC p15, 0, <Rd>, c15, c2, 0 ; Read Build Options 1 Register 

c15, Build Options 2 Register

The Build Options 2 Register characteristics are:

Purpose

Reflects the build configuration options used to build the processor.

Usage constraints

The Build Options 2 Register is:

  • a read-only register

  • accessible in Privileged mode only.

  • pin-configuration options are shown in a separate register, see Pin Options Register.

Configurations

Available in all processor configurations.

Attributes

Table 4.59 shows the bit arrangement for the Build Options 2 Register.

Figure 4.56. Build Options 2 Register bit assignments

To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.


Table 4.59 shows how the bit values correspond with the Build Options 2 Register.

Table 4.59. Build Options 2 Register bit assignments

BitsNameFunction
[31]NUM_CPU

Indicates the number of CPUs:

0 = single CPU

1 = twin CPU.

[30]LOCK_STEP

Indicates whether the CPU has redundant logic running in lock step for checking purposes:

0 = no redundant logic

1 = redundant logic included.

[29]NO_ICACHE

Indicates whether the CPU contains instruction cache:

0 = CPU contains instruction cache

1 = CPU does not contain instruction cache.

[28]NO_DCACHE

Indicates whether the CPU contains data cache:

0 = CPU contains data cache

1 = CPU does not contain data cache.

[27:26]ATCM_ES

Indicates whether an error scheme is implemented on the ATCM interface:

00 = no error scheme

10 = 32-bit error detection and correction

11 = 64-bit error detection and correction.

[25:24]BTCM_ES

Indicates whether an error scheme is implemented on the BTCM interface(s):

00 = no error scheme

10 = 32-bit error detection and correction

11 = 64-bit error detection and correction.

[23]NO_IE

Indicates whether the processor supports big-endian instructions:

0 = processor supports big-endian instructions

1 = processor does not support big-endian instructions.

[22]NO_FPU

Indicates whether the CPU contains a floating point unit:

0 = CPU contains a floating point unit

1 = CPU does not contain a floating point unit.

[21:20]MPU_REGIONS

Indicates the number of regions in the included CPU MPU:

0b00 = no regions, the MPU has not been included

0b10 = MPU included, with 12 regions

0b11 = MPU included, with 16 regions.

[19:17]BREAK_POINTS

Indicates the number of break points implemented in each CPU in the processor, minus 1.

[16:14]WATCH_POINTS

Indicates the number of watch points implemented in each CPU in the processor, minus 1.

[13]NO_A_TCM_INF

Indicates whether the CPUs contain ATCM ports

0 = CPUs contain ATCM ports

1 = CPUs do not contain ATCM ports.

[12]NO_B0_TCM_INF

Indicates whether the CPUs contain B0TCM ports:

0 = CPUs contain B0TCM ports

1 = CPUs do not contain B0TCM ports.

[11]NO_B1_TCM_INF

Indicates whether the CPUs contain B1TCM ports:

0 = CPUs contain B1TCM ports

1 = CPUs do not contain B1TCM ports.

[10]TCMBUSPARITY

Indicates whether the processor contains TCM address bus parity logic:

0 = processor does not contain TCM address bus parity logic

1 = processor contains TCM address bus parity logic.

[9]NO_SLAVE

Indicates whether the CPU contains an AXI slave port:

0 = CPU contains an AXI slave port

1 = CPU does not contain an AXI slave port.

[8:7]ICACHE_ES

Indicates whether an error scheme is implemented for the instruction cache:

0b00 = no error scheme

0b01 = 8-bit parity error detection

0b11 = 64-bit error detection and correction.

If the CPU does not contain an I-Cache, these bits are set to 0b00.

[6:5]DCACHE_ES

Indicates whether an error scheme is implemented for the data cache:

0b00 = no error scheme

0b01 = 8-bit parity error detection

0b10 = 32-bit error detection and correction.

If the CPU does not contain a D-Cache, these bits are set to 0b00.

[4]NO_HARD_ERROR_CACHE

Indicates whether the processor contains cache for corrected TCM errors:

0 = processor contains TCM error cache

1 = processor does not contain TCM error cache.

[3]AXI_BUS_ECC

Indicates whether the processor contains AXI bus ECC logic.

0 = processor does not contain AXI bus ECC logic

1 = processor contains AXI bus ECC logic.

[2]SL

Indicates whether the processor has been built with split/lock logic:

0 = no split/lock logic

1 = split/lock logic included.

[1]AHB_PP

Indicates whether the CPU contain AHB peripheral interfaces:

0 = CPUs do not have AHB peripheral interfaces

1 = CPUs have AHB peripheral interfaces.

[0]MICRO_SCU

Indicates whether the processor contains an ACP interface:

0 = processor does not contain ACP logic

1 = processor does contain ACP logic.


To access the Build Options 2 Register, read CP15 with:

MRC p15, 0, <Rd>, c15, c2, 1 ; Read Build Options 2 Register 
Copyright © 2010-2011 ARM. All rights reserved.ARM DDI 0460C
Non-ConfidentialID021511