B.20. Floating-point load/store instructions

This section describes the cycle timing behavior for all load and store instructions that operate on the VFP register file:

Table B.25 shows the number of cycles and result latencies for single load and store instructions and load multiple instructions. Values are shown for each instruction with and without base register writeback, and with different starting address alignments. Cycle counts and base register result latencies for store multiple instructions are the same as for the equivalent load multiple instruction.

Table B.25. Floating-point load/store instructions cycle timing behavior

Example instructionCycles/ memory cyclesCycles with writeback (!)Result latency (load)Result latency (base register, <Rn>)Comments
VLDR.32 <Sd>, [<Rn>{, #+/-<imm>}]1-1--
VLDR.64 <Dd>, [<Rn>{, #+/-<imm>}]1-1-64-bit aligned address
VLDR.64 <Dd>, [<Rn>{, #+/-<imm>}]2-2-Not aligned
VSTR.32 <Sd>, [<Rn>{, #+/-<imm>}]1----
VSTR.64 <Dd>, [<Rn>{, #+/-<imm>}]1---64-bit aligned address
VSTR.64 <Dd>, [<Rn>{, #+/-<imm>}]2---Not aligned
First address 64-bit aligned    
 VLDM{mode}.32 <Rn>{!}, {s1}1111-
 VLDM{mode}.32 <Rn>{!}, {s1,s2}121,12-
 VLDM{mode}.32 <Rn>{!}, {s1-s3}221,1,22-
 VLDM{mode}.32 <Rn>{!}, {s1-s4}231,1,2,23-
 VLDM{mode}.64 <Rn>{!}, {d1}1212-
 VLDM{mode}.64 <Rn>{!}, {d1,d2}231,23-
 VLDM{mode}.64 <Rn>{!}, {d1-d3}341,2,34-
 VLDM{mode}.64 <Rn>{!}, {d1-d4}451,2,3,45-
First address not 64-bit aligned    
 VLDM{mode}.32 <Rn>{!}, {s1}1111-
 VLDM{mode}.32 <Rn>{!}, {s1,s2}221,22-
 VLDM{mode}.32 <Rn>{!}, {s1-s3}231,2,23-
 VLDM{mode}.32 <Rn>{!}, {s1-s4}331,2,2,33-
 VLDM{mode}.64 <Rn>{!}, {d1}2222-
 VLDM{mode}.64 <Rn>{!}, {d1,d2}332,33-
 VLDM{mode}.64 <Rn>{!}, {d1-d3}442,3,44-
 VLDM{mode}.64 <Rn>{!}, {d1-d4}552,3,4,55-

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