12.5.6. Debug Identification Registers

The Debug Identification Registers are read-only registers that consist of the Peripheral Identification Registers and the Component Identification Registers. The Peripheral Identification Registers provide standard information that all CoreSight components require. Only bits [7:0] of each register are used. The remaining bits Read-As-Zero.

The Component Identification Registers identify the processor as a CoreSight component. Only bits [7:0] of each register are used, the remaining bits Read-As-Zero. The values in these registers are fixed.

Table 12.30 shows the offset value, register number, and description that are associated with each Peripheral Identification Register.

Table 12.30. Peripheral Identification Registers

Offset (hex)Register numberFunction
0xFD01012Peripheral Identification Register 4
0xFD41013Reserved
0xFD81014Reserved
0xFDC1015Reserved
0xFE01016Peripheral Identification Register 0
0xFE41017Peripheral Identification Register 1
0xFE81018Peripheral Identification Register 2
0xFEC1019Peripheral Identification Register 3

Table 12.31 shows fields that are in the Peripheral Identification Registers.

Table 12.31. Fields in the Peripheral Identification Registers

Field

SizeDescription
4KB Count4 bitsIndicates the Log2 of the number of 4KB blocks occupied by the debug device. The processor debug registers occupy a single 4KB block, therefore this field is always 0x0.
JEP106 Identity Code4+7 bitsIdentifies the designer of the processor. This field consists of a 4-bit continuation code and a 7-bit identity code. Because the processor is designed by ARM, the continuation code is 0x4 and the identity code is 0x3B. For more information see JEP106M, Standard Manufacture’s Identification Code.
Part number12 bitsIndicates the part number of the processor. The part number for the processor is 0xC15.
Revision4 bits

Indicates the major and minor revision of the product. The major revision contains functionality changes and the minor revision contains bug fixes for the product. The revision number starts at 0x0 and increments by 1 at both major and minor revisions:

0x0 = r0p0

0x1 = r1p0

0x2 = r1p1.

RevAnd4 bitsIndicates the manufacturer revision number. This number starts at 0x0 and increments by the integrated circuit manufacturer on metal fixes. For the Cortex-R5 processor, the initial value is 0x0 but this value can be changed by the manufacturer.
Customer modified4 bitsIndicates an endorsed modification to the device. On this processor the value is always 0x0.

Table 12.32 shows how the bit values correspond with the Peripheral ID Register 0 functions.

Table 12.32. Peripheral ID Register 0 functions

BitsValueDescription

[31:8]

-

Reserved

[7:0]

0x15

Indicates bits [7:0] of the Part number for the processor


Table 12.33 shows how the bit values correspond with the Peripheral ID Register 1 functions.

Table 12.33. Peripheral ID Register 1 functions

BitsValueDescription

[31:8]

-

Reserved

[7:4]

0xB

Indicates bits [3:0] of the JEDEC JEP106 Identity Code

[3:0]

0xC

Indicates bits [11:8] of the Part number for the processor


Table 12.34 shows how the bit values correspond with the Peripheral ID Register 2 functions.

Table 12.34. Peripheral ID Register 2 functions

BitsValueDescription

[31:8]

-

Reserved.

[7:4]

-

Indicates the revision number for the Cortex-R5 processor. This is the major revision number n in the rn part of the rnpn description of the product revision status.

[3]

0x1

This field is always set to 1. It indicates that the processor uses a JEP 106 identity code.

[2:0]

0x3

Indicates bits [6:4] of the JEDEC JEP106 Identity Code.


Table 12.35 shows how the bit values correspond with the Peripheral ID Register 3 functions.

Table 12.35. Peripheral ID Register 3 functions

BitsValueDescription

[31:8]

-

Reserved.

[7:4]

0x0

Indicates the manufacturer revision number. This value changes based on the metal fixes made by the manufacturer.

[3:0]

0x0

Customer modified. See Table 12.31.


Table 12.36 shows how the bit values correspond with the Peripheral ID Register 4 functions.

Table 12.36. Peripheral ID Register 4 functions

BitsValueDescription

[31:8]

-

Reserved.

[7:4]

0x0

Indicates the number of blocks the debug component occupies. This field is always set to 0.

[3:0]

0x4

Indicates the JEDEC JEP106 continuation code. For the processor, this value is 4.

Table 12.37 shows the offset value, register number, and value that are associated with each Component Identification Register.

Table 12.37. Component Identification Registers

Offset (hex)Register numberValueDescription
0xFF010200x0DComponent Identification Register 0
0xFF410210x90Component Identification Register 1
0xFF810220x05Component Identification Register 2
0xFFC10230xB1Component Identification Register 3

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