9.6. Accessing RAMs using the AXI slave
interface
This section describes how to access the TCM and cache RAMs
using the AXI slave interface.
Table 9.25 shows
the bits of the ARCSELSm or AWCSELSm inputs, that determine the
target of a transaction. Each signal is a one-hot 4-bit input, with
each bit corresponding to a particular RAM or group of RAMs.
Table 9.25. RAM region decode
| AxCSELSm bit | One-hot RAM select |
|---|
| [3] | Data cache RAMs |
| [2] | Instruction cache RAMs |
| [1] | B0TCM and B1TCM |
| [0] | ATCM |
The remaining addressing information is encoded in ARADDRSm[22:0] for reads and AWADDRSm[22:0] for writes. The AXI-slave
interface does not use the other bits of the address, ARADDRSm[31:23] and AWADDRSm[31:23],
except for the purposes of bus-ECC. For more information see:
Note
Because AWCSELSm and AWADDRSm are similar to ARCSELSm and ARADDRSm,
the following sections describe their common features as AxCSELSm and AxADDRSm,
noting any differences between them.
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