9.5. Enabling or disabling AXI slave accesses

This section describes how to enable or disable AXI slave accesses to the cache RAMs. When caches are accessible by the AXI slave interface, the caches are considered to be cache-off from the processor. You must ensure that the ACP is idle so that it does not generate any cache RAM accesses. After turning the interface on or off, an ISB instruction must flush the pipeline so that all subsequent instruction fetches return valid data.

The following code is an example of enabling AXI slave accesses to the cache RAMs:

MRC p15, 0, R1, c1, c0, 1  ; Read Auxiliary Control Register
ORR R1, R1, #0x1 <<24
; Ensure ACP is idle, that is. cannot access the cache and that no new ACP transactions
; can be generated
DSB
MCR p15, 0, R1, c1, c0, 1  ; enabled AXI slave accesses to the cache RAMs
ISB
; Clean entire data cache. This routine depends on the data cache size. It can be
; omitted if it is known that the data cache has no dirty data 
Fetch from uncached memory
Fetch from uncached memory
Fetch from uncached memory
Fetch from uncached memory

The following code is an example of disabling AXI slave accesses to the cache RAMs. No cache invalidation is performed because it is assumed that, after accessing the cache RAMs, the AXI slave interface restored the previously valid data to them.

MRC p15, 0, R1, c1, c0, 1    ; Read Auxiliary Control Register
BIC R1, R1, #0x1 <<24
DSB
MCR p15, 0, R1, c1, c0, 1    ; disabled AXI slave accesses to the cache RAMs
ISB
; Re-enable ACP transactions
Fetch from cached memory
Fetch from cached memory
Fetch from cached memory
Fetch from cached memory
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