9.3.3. Linefills

Loads and instruction fetches from Normal, Cacheable memory that do not hit in the cache generate a cache linefill when the appropriate cache is enabled. Table 9.11 shows the values of ARADDRMm, ARBURSTMm, ARSIZEMm, and ARLENMm for cache linefills.

Table 9.11. Linefill behavior on the AXI interface

0x00-0x070x00Wrap64-bit4 data transfers
0x08-0x0F0x08Wrap64-bit4 data transfers
0x10-0x170x10Wrap64-bit4 data transfers
0x18-0x1F0x18Wrap64-bit4 data transfers

[a] These are the bottom five bits of the address of the access that cause the linefill, that is, the address of the critical word.

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