9.6.1. TCM RAM access

AxADDRSm[22:3] indicates the address of the doubleword within the TCM that you want to access. If you are accessing a TCM that is smaller than the maximum 8MB, then it is possible to describe an address that is outside of the physical size of the TCM. This is not permitted and results in a SLVERR error response.

Table 9.26 shows the decode of the AxCSELSm[3:0] signal, and the state of the address signals for accessing different TCM RAMs. The table also shows the SLBTCMSBm configuration input signal that determines which address bit is used to select between the banks of a dual-banked BTCM.

Table 9.27 shows the most significant bit of the address for the different TCM RAM sizes. For split BTCMs, the TCM size is defined to be the total size of both the B0TCM and B1TCM combined. In this situation, the particular BTCM accessed is dependent on either AxADDRSm[MSB], if the input SLBTCMSBm is high, or AxADDRSm[3] otherwise. For example, if there are split BTCMs and SLBTCMSBm is LOW and AxADDRSm[3] is HIGH, the access goes to the B1TCM.

Table 9.26. TCM chip-select decode

AxCSELSm[3:0]BTCM portsSLBTCMSBmAxADDRSm[3]AxADDRSm[MSB]RAM selected
0001----ATCM
00101---BTCM
0010200-B0TCM
0010201-B1TCM
001021-0B0TCM
001021-1B1TCM

Table 9.27. MSB bit for the different TCM RAM sizes

TCM sizeAxADDRSm[MSB]
4KB[11]
8KB[12]
16KB[13]
32KB[14]
64KB[15]
128KB[16]
256KB[17]
512KB[18]
1MB[19]
2MB[20]
4MB[21]
8MB[22]

An access to the TCM RAMs is given a SLVERR error response if:

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