9.2. AXI master interface

The processor has a single AXI master interface, with one port that is used for:

The port is 64 bits wide, and conforms to the AXI3 standard as described in the AMBA AXI Protocol Specification. Within the AXI standard, the master port uses a number of extension signals to indicate inner memory attributes and, if configured with bus-ECC, parity or ECC information. See AXI extensions for more information about attribute encodings and Bus ECC for more information about bus-ECC.

The master interface can run at the same frequency as the processor or at a lower synchronous frequency. See AMBA interface clocking for more information.


References in this section to an AXI slave refer to the AXI slave in the external system that is connected to the Cortex-R5 AXI master port. This is not necessarily the Cortex-R5 AXI slave port.

The following sections describe the attributes of the AXI master interface, and provide information about the types of burst generated:

Table 9.1 shows the AXI master interface attributes.

Table 9.1. AXI master interface attributes

Write issuing capability4 Made up of four outstanding writes that can be evictions, single writes, or write bursts.[a]
Read issuing capability7 Made up of five linefills on the data side, one NC read on the data side, and one read on the instruction side, that can be NC or linefill.
Combined issuing capability11[a]-
Write ID capability2-
Write interleave capability 1The AXI master interface presents all write data in order.
Read ID capability7Made up of five linefills on the data side, one NC read on the data side, and one linefill or NC read on the instruction side.

[a] When there are three outstanding write transactions, only data is issued for the fourth. Only three outstanding write addresses are issued.

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