13.3.6. Integration Mode Control Register (DBGITCTRL)

The DBGITCTRL Register, register 0x3C0 at offset 0xF00, is read/write. Figure 13.4 shows the register bit assignments.

Figure 13.4. DBGITCTRL Register bit assignments

To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.


Table 13.7 shows the fields of the DBGITCTRL Register.

Table 13.7. DBGITCTRL Register bit assignments

BitsAccessNameFunction
[31:1]RAZ/SBZP-Reserved.
[0]R/WINTMODE

Controls whether the processor is in normal operating mode or integration mode:

b0 = normal operation, this is the reset value

b1 = integration mode enabled.


Writing to the DBGITCTRL register controls whether the processor is in its default functional mode, or in integration mode, where the inputs and outputs of the device can be directly controlled for the purpose of integration testing or topology detection. For more information see the ARM Architecture Reference Manual.

Copyright © 2010-2011 ARM. All rights reserved.ARM DDI 0460C
Non-ConfidentialID021511