Cortex-R5 and Cortex-R5F Technical Reference ManualRevision: r1p1
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12.4.8. Debug State Cache Control Register

The DBGDSCCR Register characteristics are:

Purpose

Controls the L1 cache behavior when the processor is in debug state.

Usage constraints

For information on the usage model of the DBGDSCCR register, see Cache debug.

Configurations

Available in all processor configurations.

Attributes

See Table 12.13.

Figure 12.8 shows the bit assignments.

Figure 12.8. DBGDSCCR Register bit assignments

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Table 12.13 shows the bit assignments.

Table 12.13. DBGDSCCR Register bit assignments

BitsName

Reset value

Description

[31:3]

-

0

Reserved. Do not modify on writes. On reads, the value returns zero.

[2]

nWT

0

Not write-through:

1 = normal operation of regions marked as write-back in debug state

0 = force write-through behavior for regions marked as write-back in debug state, this is the reset value.

[1]

nIL0

Instruction cache line-fill:

1 = normal operation of L1 instruction cache in debug state

0 = L1 instruction cache line-fills disabled in debug state, this is the reset value.

[0]

nDL

0

Data cache line-fill:

1 = normal operation of L1 data cache in debug state

0 = L1 data cache line-fills disabled in debug state, this is the reset value.


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