Cortex-R5 and Cortex-R5F Technical Reference ManualRevision: r1p1
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12.3.3. Coprocessor registers summary

Table 12.2 shows a set of valid CP14 instructions for accessing the debug registers. All CP14 instructions not listed are Undefined.

Note

The CP14 debug instructions are defined as having Opcode_1 set to 0.

Table 12.2. CP14 debug registers summary

InstructionMnemonicDescription
MRC p14, 0, <Rd>, c0, c0, 0DBGDIDRDebug Identification Register. See CP14 c0, Debug ID Register.
MRC p14, 0, <Rd>, c1, c0, 0DBGDRARDebug ROM Address Register. See CP14 c0, Debug ROM Address Register.
MRC p14, 0, <Rd>, c2, c0, 0DBGDSARDebug Self Address Register. See CP14 c0, Debug Self Address Offset Register.
MRC p14, 0, <Rd>, c0, c5, 0

STC p14, c5, <addressing mode>
DBGDTRRXintHost to Target Data Transfer Register. See Data Transfer Register.
MCR p14, 0, <Rd>, c0, c5, 0

LDC p14, c5, <addressing mode>
DBGDTRTXintTarget to Host Data Transfer Register. See Data Transfer Register.
MRC p14, 0, <Rd>, c0, c1, 0

MRC p14, 0, APSR_nzcv, c0, c1, 0
DBGDSCRintDebug Status and Control Register. See CP14 c1, Debug Status and Control Register.

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