12.4.10. Debug Run Control Register

The DBGDSCR Register characteristics are:

Purpose
  • Requests the processor to enter or leave debug state.

  • Clears the sticky exception bits present in the DBGDSCR.

Usage constraints

The DBGDRCR is a write-only register.

Configurations

Available in all processor configurations.

Attributes

Figure 12.9 shows the bit assignments.

Figure 12.9. DBGDRCR Register bit assignments

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Table 12.14 shows the bit assignments.

Table 12.14. DBGDRCR Register functions

BitsNameFunction

[31:5]

-

RAZ.

[4]

Cancel memory requests

If 1 is written to this bit, the processor abandons any pending memory transactions until it can enter debug state. Debug state entry is the acknowledge event that clears this request. Abandoned transactions have the following behavior:

  • abandoned stores might write an Unpredictable value to the target address

  • abandoned loads return an Unpredictable value to the register bank.

An abandoned transaction does not cause any exception. Additional instruction fetches or data accesses after the processor entered debug state have an Unpredictable behavior.

This bit enables the debugger to progress on a deadlock so the processor can enter debug state. For a debug state entry to occur, a halting debug event must be requested before this bit is set. If you write a 1 to this bit when DBGENm is LOW, the write has no effect.[a]

[3]

Clear sticky pipeline advance

Writing a 1 to this bit clears DBGDSCR[25].

[2]

Clear sticky exceptions

Writing a 1 to this bit clears DBGDSCR[8:6].

[1]

Restart request

Writing a 1 to this bit requests that the processor leaves debug state. This request is held until the processor exits debug state. When the debugger makes this request, it polls DBGDSCR[1] until it reads 1. This bit always reads as zero. Writes are ignored when the processor is not in debug state.

[0]

Halt request

Writing a 1 to this bit triggers a halting debug event, that is, a request that the processor enters debug state. This request is held until the debug state entry occurs. When the debugger makes this request, it must poll DBGDSCR[0] until it reads 1. This bit always reads as zero. Writes are ignored when the processor is already in debug state.

[a] Entry into debug state is not expected to be recoverable.


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