Cortex-R5 and Cortex-R5F Technical Reference Manual: 12.5. Management registers

12.5. Management registers

The Management Registers define the standardized set of registers that all CoreSight components implement. This section describes these registers.

Table 12.24 shows the contents of the Management Registers for the processor debug unit.

Table 12.24. Management Registers

Offset (hex)	Register number	Access	Mnemonic	Description
`0xD00-0xDFC`	832-895	R	-	See Processor ID Registers.
`0xF00`	960	RW	DBGITCTRL	See Integration Mode Control Register (DBGITCTRL).
`0xFA0`	1000		DBGCLAIMSET	See Claim Tag Set Register.
`0xFA4`	1001		DBGCLAIMCLR	See Claim Tag Clear Register .
`0xFB0`	1004	W	DBGLAR	See Lock Access Register.
`0xFB4`	1005	R	DBGLSR	See Lock Status Register.
`0xFB8`	1006	R	DBGAUTHSTATUS	See Authentication Status Register.
`0xFB8-0xFC4`	1006-1009	R	-	Reserved.
`0xFC8`	1010	R	DBGDEVID	Device Identifier. Reserved.
`0xFCC`	1011	R	DBGDEVTYPE	See Device Type Register.
`0xFD0-0xFFC`	1012-1023	R	-	See Debug Identification Registers.

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