12.4.12. Breakpoint Control Registers

The DBGBCR Register characteristics are:

Purpose

Contains the necessary control bits for setting:

  • breakpoints

  • linked breakpoints.

Usage constraints

There are no usage constraints.

Configurations

Available in all processor configurations.

Attributes

Figure 12.10 shows the bit assignments.

Figure 12.10. DBGBCR Registers bit assignments

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Table 12.16 shows the bit assignments.

Table 12.16. Breakpoint Control Register bit assignments

BitsNameFunction

[31:29]

-

Do not modify on writes. On reads, the value returns zero.

[28:24]

Breakpoint address mask

This field sets a breakpoint on a range of addresses by masking lower order address bits out of the breakpoint comparison.[a]

b00000 = no mask

b00001 = Reserved

b00010 = Reserved

b00011 = 0x00000007 mask for instruction address

b00100 = 0x0000000F mask for instruction address

b00101 = 0x0000001F mask for instruction address

...

b11111 = 0x7FFFFFFF mask for instruction address.

[23]

--

[22:20]

M

Meaning of DBGBVR:

b000 = instruction address match

b001 = linked instruction address match

b010 = unlinked context ID

b011 = linked context ID

b100 = instruction address mismatch

b101 = linked instruction address mismatch

b11x = Reserved.

For more information, see Table 12.17

[19:16]

Linked BRP number

The binary number encoded here indicates another BRP to link this one with.

Note

  • if a BRP is linked with itself, it is Unpredictable whether a breakpoint debug event is generated

  • if this BRP is linked to another BRP that is not configured for linked context ID matching, it is Unpredictable whether a breakpoint debug event is generated.

[15:14]

Secure state access controlRAZ or SBZP.

[13:9]

-

Do not modify on writes. On reads, the value returns zero.

[8:5]

Byte address select

For breakpoints programmed to match an instruction address, the debugger must write a word-aligned address to the DBGBVR. You can then use this field to program the breakpoint so it hits only if certain byte addresses are accessed.[b]

If the BRP is programmed for instruction address match:

b0000 = the breakpoint never hits

bxxx1 = the breakpoint hits if the byte at address (DBGBVR & 0xFFFFFFFC) +0 is accessed

bxx1x = the breakpoint hits if the byte at address (DBGBVR & 0xFFFFFFFC) +1 is accessed

bx1xx = the breakpoint hits if the byte at address (DBGBVR & 0xFFFFFFFC) +2 is accessed

b1xxx = the breakpoint hits if the byte at address (DBGBVR & 0xFFFFFFFC) +3 is accessed

b1111 = the breakpoint hits if any of the four bytes starting at address (DBGBVR & 0xFFFFFFFC) +0 is accessed.

If the BRP is programmed for instruction address mismatch, the breakpoint hits where the corresponding instruction address breakpoint does not hit, that is, the range of addresses covered by an instruction address mismatch breakpoint is the negative image of the corresponding instruction address breakpoint.

If the BRP is programmed for context ID comparison, this field must be set to b1111. Otherwise, breakpoint and watchpoint debug events might not be generated as expected.

[4:3]

--

[2:1]

S

Supervisor access control. The breakpoint can be conditioned on the mode of the processor:

b00 = User, System, or Supervisor

b01 = Privileged

b10 = User

b11 = any.

[0]

B

Breakpoint enable:

0 = Breakpoint disabled. This is the reset value.

1 = Breakpoint enabled.

[a] If DBGBCR[28:24] is not set to b00000, then DBGBCR[8:5] must be set to b1111. Otherwise the behavior is Unpredictable. In addition, if DBGBCR[28:24] is not set to b00000, then the corresponding DBGBVR bits that are not being included in the comparison Should Be Zero. Otherwise the behavior is Unpredictable. If this BRP is programmed for context ID comparison, this field must be set to b00000. Otherwise the behavior is Unpredictable. There is no encoding for a full 32-bit mask but the same effect of a break anywhere breakpoint can be achieved by setting DBGBCR[22] to 1 and DBGBCR[8:5] to b0000.

[b] Writing a value to DBGBCR[8:5] so that DBGBCR[8] is not equal to DBGBCR[7] or DBGBCR[6] is not equal to DBGBCR[5] has Unpredictable results.


Table 12.17. Meaning of DBGBVR bits [22:20]

DBGBVR[22:20]Meaning
b000

The corresponding DBGBVR[31:2] is compared against the instruction address bus and the state of the processor against this DBGBCR. It generates a breakpoint debug event on a joint instruction address and state match.

b001

The corresponding DBGBVR[31:2] is compared against the instruction address bus and the state of the processor against this DBGBCR. This BRP is linked with the one indicated by DBGBCR[19:16] linked BRP field. They generate a breakpoint debug event on a joint instruction address, context ID, and state match.

b010

The corresponding DBGBVR[31:0] is compared against CP15 Context ID Register, c13 and the state of the processor against this DBGBCR. This BRP is not linked with any other one. It generates a breakpoint debug event on a joint context ID and state match. For this BRP, DBGBCR[8:5] must be set to b1111. Otherwise it is Unpredictable whether a breakpoint debug event is generated.

b011

The corresponding DBGBVR[31:0] is compared against CP15 Context ID Register, c13. This BRP links another BRP (of the DBGBCR[21:20]=b01 type), or WRP (with DBGWCR[20]=b1). They generate a breakpoint or watchpoint debug event on a joint instruction address or data address and context ID match. For this BRP, DBGBCR[8:5] must be set to b1111, DBGBCR[15:14] must be set to b00, and DBGBCR[2:1] must be set to b11. Otherwise it is Unpredictable whether a breakpoint debug event is generated.

b100

The corresponding DBGBVR[31:2] and DBGBCR[8:5] are compared against the instruction address bus and the state of the processor against this DBGBCR. It generates a breakpoint debug event on a joint instruction address mismatch and state match.

b101

The corresponding DBGBVR[31:2] and DBGBCR[8:5] are compared against the instruction address bus and the state of the processor against this DBGBCR. This BRP is linked with the one indicated by DBGBCR[19:16] linked BRP field. It generates a breakpoint debug event on a joint instruction address mismatch, state and context ID match.

b11xReserved. The behavior is Unpredictable.

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