12.4.1. CP14 c0, Debug ID Register

The DBGDIDR Register characteristics are:

Purpose

Identifies the debug architecture version and specifies the number of debug resources that the processor implements.

Usage constraints

The DBGDIDR is:

  • in CP14 c0

  • a 32 bit read-only register

  • accessible in User and Privileged modes.

Configurations

Available in all processor configurations.

Attributes

Figure 12.2 shows the bit assignments.

Figure 12.2. DBGDIDR Register bit assignments

To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.


Table 12.6 shows the bit assignments.

Table 12.6. DBGDIDR Register bit assignments

BitsNameFunction

[31:28]

WRP

Number of Watchpoint Register Pairs:

b0000 = 1 WRP

b0001 = 2 WRPs

...

b0111 = 8 WRPs.

[27: 24]

BRP

Number of Breakpoint Register Pairs:

b0001 = 2 BRPs

b0010 = 3 BRPs

...

b0111 = 8 BRPs.

[23:20]

Context

Number of Breakpoint Register Pairs (BRP) with context ID comparison capability:

b0000 = 1 BRP has context ID comparison capability.

[19:16]

Debug architecture version

Debug architecture version:

b0100 denotes ARMv7 Debug.

[15]DEVID_imp

Indicates whether DBGDEVID is implemented.

0 = not implemented, register 1010 is reserved.

[14]nSUHD_impRAZ.
[13]PCSR_imp RAZ.
[12]SE_imp RAZ.

[11:8]

-

RAZ.

[7: 4]

Variant

Implementation-defined variant number.This is the major revision number n in the rn part of the rnpn description of the product revision status.

[3: 0]

Revision

Implementation-defined revision number. This is the minor revision number n in the pn part of the rnpn description of the product revision status.


The values of the following fields of the DBGDIDR agree with the values in CP15 c0, Main ID Register:

See c0, Main ID Register for more information of CP15 c0, Main ID Register.

The reason for duplicating these fields here is that the DBGDIDR is also accessible through the APB slave port. This enables an external debugger to determine the variant and revision numbers without stopping the processor.

To use the DBGDIDR, read CP14 c0 with:

MRC p14, 0, <Rd>, c0, c0, 0 ; Read DBGDIDR
Copyright © 2010-2011 ARM. All rights reserved.ARM DDI 0460C
Non-ConfidentialID021511