12.4.7. Vector Catch Register

The DBGVCR Register characteristics are:

Purpose

Controls efficient exception vector catching.

Usage constraints
  • If one of the bits in this register is set and the instruction at the corresponding vector is committed for execution, the processor either enters debug state or takes a debug exception.

  • Under this model, any prefetch from an exception vector can trigger a vector catch, not only the ones because of exception entries. An explicit branch to an exception vector might generate a vector catch debug event.

  • If any of the bits are set when the processor is in Monitor debug-mode, then the processor ignores the setting and does not generate a vector catch debug event. This prevents the processor entering an unrecoverable state. The debugger must program these bits to zero when Monitor debug-mode is selected and enabled to ensure forward-compatibility.

Configurations

Available in all processor configurations.

Attributes

as Figure 12.7 shows.

Figure 12.7. DBGVCR Register bit assignments

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Table 12.12 shows the bit assignments.

Table 12.12. DBGVCR Register bit assignments

BitsName

Reset value

Normal address

High vectors address

FunctionAccess
[31:8]-0--Do not modify on writes. On reads, the value returns zero.RAZ or SBZP
[7]FIQ00x0000001C0xFFFF001C

Vector catch enable, FIQ.

RW
[6]IRQ-0x00000018[a]0xFFFF0018[a]Vector catch enable, IRQ.-
[5]-0--Do not modify on writes. On reads, the value returns zero.RAZ or SBZP
[4]Data Abort00x000000100xFFFF0010Vector catch enable, data abort.RW
[3]Prefetch Abort00x0000000C0xFFFF000CVector catch enable, prefetch abort.RW
[2]SVC00x000000080xFFFF0008Vector catch enable, SVC.RW
[1]Undefined00x000000040xFFFF0004Vector catch enable, Undefined Instruction.RW
[0]Reset00x000000000xFFFF0000Vector catch enable, reset.RW

[a] If the VIC interface is enabled, the address is the last IRQ handler address supplied by the VIC, whether or not high vectors are in use.


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