12.4.17. Device Power-down and Reset Control Register

The DBGPRCR Register characteristics are:


Controls reset and power-down related functionality.

Usage constraints

The DBGPRCR Register is read-write with more restricted access to some bits.


Available in all processor configurations.


Figure 12.14 shows the bit assignments.

Figure 12.14. DBGPRCR Register bit assignments

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Table 12.22 shows the bit assignments.

Table 12.22. DBGPRCR Register bit assignments




Do not modify on writes. On reads, the value returns zero.


Hold internal reset

Hold internal reset bit. This bit can be used to prevent the processor from running again before the debugger detects a power-down event and restores the state of the debug registers in the processor. This bit does not have any effect on initial system power-up, because nSYSPORESET clears it.

0 = Do not hold internal reset on power-up or warm reset. This is the reset value.

1 = Hold the processor non-debug logic in reset on warm reset until this flag is cleared.


Force internal resetWhen a 1 is written to this bit, the processor asserts the DBGRSTREQm output for four cycles. You can connect this output to an external reset controller that, in turn, resets the processor.


No power-down

When set to 1, the DBGNOPWRDWN output signal is HIGH. This output connects to the system power controller and is interpreted as a request to operate in emulate mode, if the system supports this functionality. In this mode, the processor is not actually powered down when requested by software or hardware handshakes. This mode is useful when debugging applications on top of working operating systems.

0 = DBGNOPWRDWN is LOW. This is the reset value


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