Cortex-R5 and Cortex-R5F Technical Reference Manual: 12.4.3. CP14 c0, Debug Self Address Offset Register

12.4.3. CP14 c0, Debug Self Address Offset Register

The DBGDSAR Register characteristics are:

Purpose

The DBGDSAR is a read-only register that returns a 32-bit offset value from the Debug ROM Address Register to the address of the CPU debug registers. You can configure the address read in this register during integration using the DBGSELFADDRm[31:12] and DBGSELFADDRVm inputs. DBGSELFADDRVm must be tied off to 1 if DBGSELFADDRm[31:12] is tied off to a valid value.

Usage constraints

The DBGDSAR is:

in CP14 c0, sub-register c2
a 32 bit read-only register
accessible in User and Privileged modes.

Configurations

Available in all processor configurations.

Attributes

See Table 12.8.

Figure 12.4 shows the bit assignments.

Figure 12.4. DBGDSAR Register bit assignments

Table 12.8 shows the bit assignments.

Table 12.8. DBGDSAR Register bit assignments

Bits	Name	Function
[31:12]	Debug bus self address offset value	Indicates bits [31:12] of the two’s complement offset from the debug ROM physical address to the physical address where the debug registers are mapped.
[11: 2]	-	UNP on reads, SBZP on writes.
[1:0]	Valid bits	Reads b11 if DBGSELFADDRVm is set to 1, otherwise reads b00. DBGSELFADDRVm must be set to 1 if DBGSELFADDRm[31:12] is set to a valid value.

To use the DBGDSAR, read CP14 c0 with:

MRC p14, 0, <Rd>, c2, c0, 0            ; Read DBGDSAR

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