12.4.2. CP14 c0, Debug ROM Address Register

The DBGDSAR Register characteristics are:

Purpose

Returns a 32-bit Debug ROM Address Register value. This is the address that indicates where in memory a debug monitor can locate the debug bus ROM specified by the CoreSight™ multiprocessor trace and debug architecture. Returns a 32-bit Debug ROM Address Register value. This is the address that indicates where in memory a debug monitor can locate the debug bus ROM specified by the CoreSight™ multiprocessor trace and debug architecture.

Usage constraints

The DBGDRAR is:

  • in CP14 c0, sub-register c1

  • a 32 bit read-only register

  • accessible in User and Privileged modes.

Configurations

Available in all processor configurations.

Attributes

Figure 12.3 shows the bit assignments.

Figure 12.3. DBGDRAR Register bit assignments

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Table 12.7 shows the bit assignments.

Table 12.7. DBGDRAR Register bit assignments

BitsNameFunction

[31:12]

Debug bus ROM address

Indicates bits [31:12] of the debug bus ROM address.

[11: 2]

-

SBZ.

[1:0]

Valid bits

Indicates that the ROM address is valid.

Reads b11 if DBGROMADDRV is set to 1, otherwise reads b00. DBGROMADDRV must be set to 1 if DBGROMADDR[31:12] is set to a valid value.


To use the DBGDRAR, read CP14 c0 with:

MRC p14, 0, <Rd>, c1, c0, 0 ; Read DBGDRAR
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