3.7.6. The GE bits

Some of the SIMD instructions set GE[3:0] as greater-than-or-equal bits for individual halfwords or bytes of the result, as Table 3.2 shows.

Table 3.2. GE[3:0] settings

  GE[3]GE[2]GE[1]GE[0]
InstructionA op B greater than or equal to CA op B greater than or equal to CA op B greater than or equal to CA op B greater than or equal to C
Signed
 

SADD16

[31:16] + [31:16] ≥ 0[31:16] + [31:16] ≥ 0[15:0] + [15:0] ≥ 0[15:0] + [15:0] ≥ 0
 

SSUB16

[31:16] - [31:16] ≥ 0[31:16] - [31:16] ≥ 0[15:0] - [15:0] ≥ 0[15:0] - [15:0] ≥ 0
 

SADDSUBX

[31:16] + [15:0] ≥ 0[31:16] + [15:0] ≥ 0[15:0] - [31:16] ≥ 0[15:0] - [31:16] ≥ 0
 

SSUBADDX

[31:16] - [15:0] ≥ 0[31:16] - [15:0] ≥ 0[15:0] + [31:16] ≥ 0[15:0] + [31:16] ≥ 0
 

SADD8

[31:24] + [31:24] ≥ 0[23:16] + [23:16] ≥ 0[15:8] + [15:8] ≥ 0[7:0] + [7:0] ≥ 0
 

SSUB8

[31:24] - [31:24] ≥ 0[23:16] - [23:16] ≥ 0[15:8] - [15:8] ≥ 0[7:0] - [7:0] ≥ 0
Unsigned
 UADD16[31:16] + [31:16] ≥ 216[31:16] + [31:16] ≥ 216[15:0] + [15:0] ≥ 216[15:0] + [15:0] ≥ 216
 USUB16[31:16] - [31:16] ≥ 0[31:16] - [31:16] ≥ 0[15:0] - [15:0] ≥ 0[15:0] - [15:0] ≥ 0
 UADDSUBX[31:16] + [15:0] ≥ 216[31:16] + [15:0] ≥ 216[15:0] - [31:16] ≥ 0[15:0] - [31:16] ≥ 0
 USUBADDX[31:16] - [15:0] ≥ 0[31:16] - [15:0] ≥ 0[15:0] + [31:16] ≥ 216[15:0] + [31:16] ≥216
 UADD8[31:24] + [31:24] ≥ 28[23:16] + [23:16] ≥ 28[15:8] + [15:8] ≥ 28[7:0] + [7:0] ≥ 28
 USUB8[31:24] - [31:24] ≥ 0[23:16] - [23:16] ≥ 0[15:8] - [15:8] ≥ 0[7:0] - [7:0] ≥ 0

Note

GE bit is 1 if A op B ≥ C, otherwise 0.

The SEL instruction uses GE[3:0] to select which source register supplies each byte of its result. See the ARM Architecture Reference Manual for more information.

Copyright © 2010-2011 ARM. All rights reserved.ARM DDI 0460C
Non-ConfidentialID021511