3.8.6. Undefined Instruction

The processor takes the Undefined Instruction exception when:

Software can use this mechanism to extend the ARM instruction set by emulating Undefined coprocessor instructions. Undefined Instruction exceptions also occur when a UDIV or SDIV instruction is executed, the value in Rm is zero, and the DZ bit in the SCTLR is set.

If the handler is required to return after the instruction that caused the Undefined Instruction exception, it must:

IRQs are disabled when an Undefined Instruction trap occurs. For more information about Undefined instructions, see the ARM Architecture Reference Manual.

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