3.11. Big-endian instruction support

The processor supports little-endian or big-endian instruction format, and is dependent on the setting of the CFGIE pin. This is reflected in bit [31] of the SCTLR. For more information, see c1, System Control Register.


The facility to use big-endian or little-endian instruction format is an implementation option, and you can therefore remove it in specific implementations. If this facility is not present, the CFGIE pin is still reflected in the SCTLR but the instruction format is always little-endian. The Build Options Register indicates whether the processor has been built with instruction endianness control. See Build Options Registers.

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