3.8.2. Reset

When the nRESETm signal is driven LOW a reset occurs, and the processor abandons the executing instruction.

When nRESETm and nCPUHALTm are driven HIGH again the processor:

  1. Forces CPSR M[4:0] to b10011 (Supervisor mode) and sets the A, I, and F bits in the CPSR. The E bit is set based on the state of the CFGEE pin. Other bits in the CPSR are indeterminate.

  2. Forces the PC to fetch the next instruction from the reset vector address.

  3. Reverts to ARM state or Thumb state depending on the state of the TEINIT pin, and resumes execution.

After reset, all register values except the PC and CPSR are indeterminate.

See Resets for more information on the reset behavior for the processor.

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