4.3.12. c0, Cache Size ID Register

The CCSIDR Register characteristics are:

Purpose

Provides information about the size and behavior of the instruction or data cache. Architecturally, there can be up to eight levels of cache, containing instruction, data, or unified caches. This processor contains L1 instruction and data caches only. The CSSELR determines which CCSIDR to select, see c0, Cache Size Selection Register.

Usage constraints

The CCSIDR is:

  • a read-only register

  • accessible in Privileged mode only.

Configurations

Available in all processor configurations.

Attributes

Figure 4.24 shows the CCSIDR bit assignments.

Figure 4.24. CCSIDR bit assignments

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Table 4.20 shows the CCSIDR bit assignments.

Table 4.20. CCSIDR bit assignments

Bits

Name Function
[31]WT

Indicates support available for write-through:

1 = write-through support available[a]

[30]WB

Indicates support available for write-back:

1 = write-back support availablea

[29]RA

Indicates support available for read allocation:

1 = read allocation support availablea

[28]WA

Indicates support available for write allocation:

1 = write allocation support availablea

[27:13]NumSets

Indicates the number of sets as

(number of sets) - 1a

[12:3]Associativity

Indicates the number of ways as

(number of ways) - 1a

[2:0]LineSizeIndicates the number of words in each cache linea

[a] See Table 4.21 for valid bit field encodings.


The LineSize field is encoded as 2 less than log(2) of the number of words in the cache line. For example, a value of 0x0 indicates there are four words in a cache line, that is the minimum size for the cache. A value of 0x1 indicates there are eight words in a cache line.

Table 4.21 shows the individual bit field and complete register encodings for the CCSIDR. Use this to match the cache size and level of cache set by the Current Cache Size Selection Register (CSSR). See c0, Cache Size Selection Register.

Table 4.21. Bit field and register encodings for CCSIDR

Size

Complete register encoding

Register bit field encoding
WTWBRAWANumSetsAssociativityLineSize
4KB0xF003E01911110x001F0x30x1
8KB0xF007E01911110x003F
16KB0xF00FE01911110x007F
32KB0xF01FE01911110x00FF
64KB0xF03FE01911110x01FF

To access the CCSIDR read CP15 with:

MRC p15, 1, <Rd>, c0, c0, 0 ; Read CCSIDR
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