Cortex-R5 and Cortex-R5F Technical Reference Manual: 4.3.23. c9, BTCM Region Register

The BTCM Region Register characteristics are:

Purpose

Usage constraints

The BTCM Region Register is:

Configurations

Available in all processor configurations.

Attributes

See Table 4.43.

Figure 4.41 shows the BTCM Region Register bit assignments.

Figure 4.41. BTCM Region Register bit assignments

Table 4.43 shows the BTCM Region Register bit assignments.

Table 4.43. BTCM Region Register bit assignments

Bits	Name	Function
[31:12]	Base address	Base address. Defines the base address of the BTCM. The base address must be aligned to the size of the BTCM. Any bits in the range [(log₂(RAMSize)-1):12] are ignored. At reset, if LOCZRAMAm is set to: 0 =The initial base address is `0x0`. 1 =The initial base address is implementation-defined. See Configurable options.
[11:7]	-	UNP on reads, SBZ on writes.
[6:2]	Size	Size. Indicates the size of the BTCM on reads. On writes this field is ignored. See About the TCMs.
[6:2]	Size	b00000 = 0KB, no TCM b00011 = 4KB b00100 = 8KB b00101 = 16KB	b00110 = 32KB b00111 = 64KB b01000 = 128KB b01001 = 256KB	b01010 = 512kB b01011 = 1MB b01100 = 2MB b01101 = 4MB b01110 = 8MB
[1]	-	SBZ.
[0]	Enable	Enables or disables the BTCM. 0 = Disabled 1 = Enabled. The reset value of this field is determined by the INITRAMBm input pin. This bit is RAZ if the processor has been implemented or integrated without a BTCM.

To access the BTCM Region Register, read or write CP15 with:

MRC p15, 0, <Rd>, c9, c1, 0  ; Read BTCM Region Register

MCR p15, 0, <Rd>, c9, c1, 0  ; Write BTCM Region Register

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