4.3.30. Validation Registers

The processor implements a set of validation registers. This section describes:

c15, nVAL IRQ Enable Set Register

The nVAL IRQ Enable Set Register characteristics are:

Purpose

Enables any of the PMXEVCNTR Registers, PMXEVCNTR0-PMXEVCNTR2, and CCNT, to generate an interrupt request on overflow. If enabled, the interrupt request is signaled by nVALIRQm being asserted LOW.

Usage constraints

The nVAL IRQ Enable Set Register is:

  • A read/write register.

  • Always accessible in Privileged mode. The PMUSERENR Register determines access in User mode, see c9, User Enable Register.

Configurations

Available in all processor configurations.

Attributes

Figure 4.44 shows the nVAL IRQ Enable Set Register bit assignments.

Figure 4.44. nVAL IRQ Enable Set Register bit assignments

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Table 4.46 shows the nVAL IRQ Enable Set Register bit assignments.

Table 4.46. nVAL IRQ Enable Set Register bit assignments

Bits

Name Function
[31]CCCNT overflow IRQ request
[30: 3]ReservedUNP or SBZP
[2]P2PMXEVCNTR2 overflow IRQ request
[1]P1PMXEVCNTR1 overflow IRQ request
[0]P0PMXEVCNTR0 overflow IRQ request

To access the nVAL IRQ Enable Set Register, read or write CP15 with:

MRC p15, 0, <Rd>, c15, c1, 0 ; Read nVAL IRQ Enable Set Register
MCR p15, 0, <Rd>, c15, c1, 0 ; Write nVAL IRQ Enable Set Register

On reads, this register returns the current setting. On writes, interrupt requests can be enabled by writing a 1 to the appropriate bits. If an interrupt request has been enabled it is disabled by writing to the nVAL IRQ Enable Clear Register, see c15, VAL IRQ Enable Clear Register.

If one or more of the IRQ request fields (P2, P1, P0, and C) is enabled, and the corresponding counter overflows, then an IRQ request is indicated by nVALIRQm being asserted LOW. This signal might be passed to a system interrupt controller.

c15, nVAL FIQ Enable Set Register

The nVAL FIQ Enable Set Register are:

Purpose

Enables any of the PMXEVCNTR Registers, PMXEVCNTR0-PMXEVCNTR2, and CCNT, to generate an fast interrupt request on overflow. If enabled, the interrupt request is signaled by nVALFIQm being asserted LOW.

Usage constraints

The nVAL FIQ Enable Set Register is:

  • A read/write register.

  • Always accessible in Privileged mode. The PMUSERENR Register determines access in User mode, see c9, User Enable Register.

Configurations

Available in all processor configurations.

Attributes

Figure 4.45 shows the nVAL FIQ Enable Set Register bit assignments.

Figure 4.45. nVAL FIQ Enable Set Register bit assignments

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Table 4.47 shows the nVAL FIQ Enable Set Register bit assignments

Table 4.47. nVAL FIQ Enable Set Register bit assignments

Bits

NameFunction
[31]CCCNT overflow FIQ request
[30:3]ReservedUNP or SBZP
[2]P2PMXEVCNTR2 overflow FIQ request
[1]P1PMXEVCNTR1 overflow FIQ request
[0]P0PMXEVCNTR0 overflow FIQ request

To access the FIQ Enable Set Register, read or write CP15 with:

MRC p15, 0, <Rd>, c15, c1, 1 ; Read FIQ Enable Set Register
MCR p15, 0, <Rd>, c15, c1, 1 ; Write FIQ Enable Set Register

On reads, this register returns the current setting. On writes, interrupt requests can be enabled by writing a 1 to the appropriate bits. If an interrupt request has been enabled it is disabled by writing to the FIQ Enable Clear Register, see c15, nVAL FIQ Enable Clear Register.

If one or more of the FIQ request fields (P2, P1, P0, and C) is enabled, and the corresponding counter overflows, then an FIQ request is indicated by nVALFIQm being asserted LOW. This signal can be passed to a system interrupt controller.

c15, nVAL Reset Enable Set Register

The nVAL Reset Enable Set Register is:

  • A read/write register.

  • Always accessible in Privileged mode. The PMUSERENR Register determines access in User mode, see c9, User Enable Register.

The nVAL Reset Enable Set Register characteristics are:

Purpose

Enables any of the PMXEVCNTR Registers, PMXEVCNTR0-PMXEVCNTR2, and CCNT, to generate a reset request on overflow. If enabled, the reset request is signaled by nVALRESETm being asserted LOW.

Usage constraints

The nVAL Reset Enable Set Register is:

  • A read/write register.

  • Always accessible in Privileged mode. The PMUSERENR Register determines access in User mode, see c9, User Enable Register.

Configurations

Available in all processor configurations.

Attributes

Figure 4.46 shows the nVAL Reset Enable Set Register bit assignments.

Figure 4.46. nVAL Reset Enable Set Register bit assignments

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Table 4.48 shows the nVAL Reset Enable Set Register bit assignments.

Table 4.48. nVAL Reset Enable Set Register bit assignments

Bits

Name Function
[31]CCCNT overflow reset request
[30:3]-UNP or SBZP
[2]P2PMXEVCNTR2 overflow reset request
[1]P1PMXEVCNTR1 overflow reset request
[0]P0PMXEVCNTR0 overflow reset request

To access the nVAL Reset Enable Set Register, read or write CP15 with:

MRC p15, 0, <Rd>, c15, c1, 2 ; Read nVAL Reset Enable Set Register
MCR p15, 0, <Rd>, c15, c1, 2 ; Write nVAL Reset Enable Set Register

On reads, this register returns the current setting. On writes, reset requests can be enabled by writing a 1 to the appropriate bits. If a reset request has been enabled, it is disabled by writing to the nVAL Reset Enable Clear Register. See c15, nVAL Reset Enable Clear Register.

If one or more of the reset request fields (P2, P1, P0, and C) is enabled, and the corresponding counter overflows, then a reset request is indicated by nVALRESETm being asserted LOW. This signal can be passed to a system reset controller.

c15, VAL Debug Request Enable Set Register

The VAL Debug Request Enable Set Register characteristics are:

Purpose

Enables any of the PMXEVCNTR Registers, PMXEVCNTR0-PMXEVCNTR2, and CCNT, to generate a debug request on overflow. If enabled, the debug request is signaled by VALEDBGRQm being asserted HIGH.

Usage constraints

The VAL Debug Request Enable Set Register is:

  • A read/write register.

  • Always accessible in Privileged mode. The PMUSERENR Register determines access in User mode, see c9, User Enable Register.

Configurations

Available in all processor configurations.

Attributes

Figure 4.47 shows the VAL Debug Request Enable Set Register bit assignments.

Figure 4.47. VAL Debug Request Enable Set Register bit assignments

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Table 4.49 shows the VAL Debug Request Enable Set Register bit assignments.

Table 4.49. VAL Debug Request Enable Set Register bit assignments

Bits

NameFunction
[31]CCCNT overflow debug request
[30:3]-UNP or SBZP
[2]P2PMXEVCNTR2 overflow debug request
[1]P1PMXEVCNTR1 overflow debug request
[0]P0PMXEVCNTR0 overflow debug request

To access the VAL Debug Request Enable Set Register, read or write CP15 with:

MRC p15, 0, <Rd>, c15, c1, 3 ; Read VAL Debug Request Enable Set Register
MCR p15, 0, <Rd>, c15, c1, 3 ; Write VAL Debug Request Enable Set Register

On reads, this register returns the current setting. On writes, debug requests can be enabled by writing a 1 to the appropriate bits. If a debug request has been enabled, it is disabled by writing to the VAL Debug Request Enable Clear Register. See c15, VAL Debug Request Enable Clear Register.

If one or more of the reset request fields (P2, P1, P0, and C) is enabled, and the corresponding counter overflows, then a debug reset request is indicated by VALEDBGRQm being asserted HIGH. This signal can be passed to an external debugger.

c15, VAL IRQ Enable Clear Register

The VAL IRQ Enable Clear Register characteristics are:

Purpose

Disables overflow IRQ requests from any of the PMXEVCNTR Registers, PMXEVCNTR0-PMXEVCNTR2, and CCNT, for which they have been enabled.

Usage constraints

The VAL IRQ Enable Clear Register is:

  • A read/write register.

  • Always accessible in Privileged mode. The PMUSERENR Register determines access in User mode, see c9, User Enable Register.

Configurations

Available in all processor configurations.

Attributes

Figure 4.48 shows the VAL IRQ Enable Clear Register bit assignments.

Figure 4.48. VAL IRQ Enable Clear Register bit assignments

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Table 4.50 shows the VAL IRQ Enable Clear Register bit assignments.

Table 4.50. VAL IRQ Enable Clear Register bit assignments

Bits

Name Function
[31]CCCNT overflow IRQ request
[30:3]-UNP or SBZP
[2]P2PMXEVCNTR2 overflow IRQ request
[1]P1PMXEVCNTR1 overflow IRQ request
[0]P0PMXEVCNTR0 overflow IRQ request

To access the VAL IRQ Enable Clear Register, read or write CP15 with:

MRC p15, 0, <Rd>, c15, c1, 4 ; Read  VAL IRQ Enable Clear Register
MCR p15, 0, <Rd>, c15, c1, 4 ; Write VAL IRQ Enable Clear Register

On reads, this register returns the current setting. On writes, overflow interrupt requests that are currently enabled can be disabled by writing a 1 to the appropriate bits.

For more information of how to enable IRQ requests on counter overflows, and how the requests are signaled, see c15, nVAL IRQ Enable Set Register.

c15, nVAL FIQ Enable Clear Register

The nVAL FIQ Enable Clear Register characteristics are:

Purpose

Disables overflow FIQ requests from any of the PMXEVCNTR Registers, PMXEVCNTR0-PMXEVCNTR2, and CCNT, that are enabled.

Usage constraints

The nVAL FIQ Enable Clear Register is:

  • A read/write register.

  • Always accessible in Privileged mode. The PMUSERENR Register determines access in User mode, see c9, User Enable Register.

Configurations

Available in all processor configurations.

Attributes

Figure 4.49 shows the nVAL FIQ Enable Clear Register bit assignments.

Figure 4.49. nVAL FIQ Enable Clear Register bit assignments

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Table 4.51 shows the nVAL FIQ Enable Clear Register bit assignments

Table 4.51. nVAL FIQ Enable Clear Register bit assignments

Bits

Name Function
[31]CCCNT overflow FIQ request
[30:3]-UNP or SBZP
[2]P2PMXEVCNTR2 overflow FIQ request
[1]P1PMXEVCNTR1 overflow FIQ request
[0]P0PMXEVCNTR0 overflow FIQ request

To access the FIQ Enable Clear Register, read or write CP15 with:

MRC p15, 0, <Rd>, c15, c1, 5 ; Read  FIQ Enable Clear Register
MCR p15, 0, <Rd>, c15, c1, 5 ; Write FIQ Enable Clear Register

On reads, this register returns the current setting. On writes, overflow interrupt requests that are enabled can be disabled by writing a 1 to the appropriate bits.

For information on how to enable FIQ requests on counter overflows, and how the requests are signaled, see c15, nVAL FIQ Enable Set Register.

c15, nVAL Reset Enable Clear Register

The nVAL Reset Enable Clear Register characteristics are:

Purpose

Disables overflow reset requests from any of the PMXEVCNTR Registers, PMXEVCNTR0-PMXEVCNTR2, and CCNT, that are enabled.

Usage constraints

The nVAL Reset Enable Clear Register is:

  • A read/write register.

  • Always accessible in Privileged mode. The PMUSERENR Register determines access in User mode, see c9, User Enable Register.

Configurations

Available in all processor configurations.

Attributes

Figure 4.50 shows the nVAL Reset Enable Clear Register bit assignments.

Figure 4.50. nVAL Reset Enable Clear Register bit assignments

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Table 4.52 shows the nVAL Reset Enable Clear Register bit assignments.

Table 4.52. nVAL Reset Enable Clear Register bit assignments

Bits

Name Function
[31]CCCNT overflow reset request
[30:3]-UNP or SBZP
[2]P2PMXEVCNTR2 overflow reset request
[1]P1PMXEVCNTR1 overflow reset request
[0]P0PMXEVCNTR0 overflow reset request

To access the nVAL Reset Enable Clear Register, read or write CP15 with:

MRC p15, 0, <Rd>, c15, c1, 6 ; Read nVAL Reset Enable Clear Register
MCR p15, 0, <Rd>, c15, c1, 6 ; Write nVAL Reset Enable Clear Register

On reads, this register returns the current setting. On writes, overflow reset requests that are enabled can be disabled by writing a 1 to the appropriate bits.

For more information of how to enable reset requests on counter overflows, and how the requests are signaled, see c15, nVAL Reset Enable Set Register.

c15, VAL Debug Request Enable Clear Register

The VAL Debug Request Enable Clear Register characteristics are:

Purpose

Disables overflow debug requests from any of the PMXEVCNTR Registers, PMXEVCNTR0-PMXEVCNTR2, and CCNT, that are enabled.

Usage constraints

The VAL Debug Request Enable Clear Register is:

  • A read/write register.

  • Always accessible in Privileged mode. The PMUSERENR Register determines access in User mode, see c9, User Enable Register.

Configurations

Available in all processor configurations.

Attributes

Figure 4.51 shows the VAL Debug Request Enable Clear Register bit assignments.

Figure 4.51. VAL Debug Request Enable Clear Register bit assignments

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Table 4.53 shows the VAL Debug Request Enable Clear Register bit assignments.

Table 4.53. VAL Debug Request Enable Clear Register bit assignments

Bits

Name Function
[31]CCCNT overflow debug request
[30:3]-UNP or SBZP
[2]P2PMXEVCNTR2 overflow debug request
[1]P1PMXEVCNTR1 overflow debug request
[0]P0PMXEVCNTR0 overflow debug request

To access the VAL Debug Request Enable Clear Register, read or write CP15 with:

                    MRC p15, 0, <Rd>, c15, c1, 7 ; Read VAL Debug Request Enable Clear Register
                    MCR p15, 0, <Rd>, c15, c1, 7 ; Write VAL Debug Request Enable Clear Register

On reads, this register returns the current setting. On writes, overflow debug requests that are enabled can be disabled by writing a 1 to the appropriate bits.

For more information of how to enable debug requests on counter overflows, and how the requests are signaled, see c15, VAL Debug Request Enable Set Register.

c15, Cache Size Override Register

The Cache Size Override Register characteristics are:

Purpose

Overwrites the caches size fields in the main register. This enables you to choose a smaller instruction and data cache size than is implemented.

Usage constraints

The Cache Size Override Register is:

  • a write-only register

  • only accessible in Privileged mode.

Configurations

Available in all processor configurations.

Attributes

Figure 4.52 shows the Cache Size Override Register bit assignments.

Figure 4.52.  Cache Size Override Register bit assignments

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Table 4.54 shows the Cache Size Override Register bit assignments.

Table 4.54.  Cache Size Override Register bit assignments

Bits

NameFunction
[31:8]-SBZ.
[7:4]Dcache

Defines the data cache size. See Table 4.55.

[3:0]Icache

Defines the instruction cache size. See Table 4.55.


Table 4.55 shows the encodings for the instruction and data cache sizes.

Table 4.55. Instruction and data cache size encodings

EncodingCache size
b00004kB
b00018kB
b001116kB
b011132kB
b111164kB

To access the Cache Size Override Register, write CP15 with:

MCR p15, 0, <Rd>, c15, c14, 0 ; Write Cache Size Override Register

Note

The VAL Cache Size Override Register can only be used to select cache sizes for which the appropriate RAM has been integrated. Larger cache sizes require deeper data and tag RAMs, and smaller cache sizes require wider tag RAMs. Therefore, it is unlikely that you can change the cache size using this register except using a simulation model of the cache RAMs. ARM recommends that you read the CCSIDR to check the actual cache sizes after writing to the Cache Size Override Register.

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