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The MPU memory region programming registers program the MPU regions.
There is one register that specifies which one of the sets of region registers is to be accessed. See c6, MPU Region Number Register. Each region has its own registers to specify:
region base address
region size and enable
region access control.
You can implement the processor with 12 or 16 regions, or without an MPU entirely. If you implement the processor without an MPU, then there are no regions and no region programming registers.
When the MPU is enabled:
The MPU determines the access permissions for all accesses to memory, including the TCMs. Therefore, you must ensure that the memory regions in the MPU are programmed to cover the complete TCM address space with the appropriate access permissions. You must define at least one of the regions in the MPU.
An access to an undefined area of memory normally generates a background fault.
For the TCM space the processor uses the access permissions but ignores the region attributes from MPU.
CP15, c9 sets the location of the TCM base address. For more information see c9, BTCM Region Register and c9, ATCM Region Register.
The MPU Region Base Address Register characteristics are:
Describes the base address of the region specified by the Memory Region Number Register.
The MPU Region Base Address Registers are:
32-bit read/write registers
accessible in Privileged mode only.
The region base address must always align to the region size.
Use these registers if the processor is configured with an MPU.
See Table 4.33.
Figure 4.34 shows the MPU Region Base Address Registers bit assignments.
Table 4.33 shows the MPU Region Base Address Registers bit assignments.
Table 4.33. MPU Region Base Address Registers bit assignments
Bits | Name | Function |
|---|---|---|
| [31:5] | Base address | Defines bits [31:5] of the base address of a region |
| [4:0] | - | SBZ |
To access an MPU Region Base Address Register, read or write CP15 with:
MRC p15, 0, <Rd>, c6, c1, 0 ; Read MPU Region Base Address Register
MCR p15, 0, <Rd>, c6, c1, 0 ; Write MPU Region Base Address Register
The MPU Region Size and Enable Register characteristics are:
Specifies the size of the region specified by the Memory Region Number Register.
Identifies the address ranges that are used for a particular region.
Enables or disables the region, and its sub-regions, specified by the Memory Region Number Register.
The MPU Region Size and Enable Registers are:
32-bit read/write registers
accessible in Privileged mode only.
Use these registers if the processor is configured with an MPU.
See Table 4.34.
Figure 4.35 shows the MPU Region Size and Enable Registers bit assignments.
Table 4.34 shows the MPU Region Size and Enable Registers bit assignments.
Table 4.34. Region Size Register bit assignments
| Bits | Name | Function | ||
|---|---|---|---|---|
| [31:16] | - | SBZ. | ||
| [15:8] | Sub-region disable | Each bit position represents a sub-region, 0-7[a]. Bit [8] corresponds to sub-region 0 ... Bit [15] corresponds to sub-region 7 The meaning of each bit is: 0 = address range is part of this region 1 = address range is not part of this region. | ||
| - | SBZ. | |||
| [5:1] | Region size | Defines the region size: b00000 - b00011=Unpredictable b00100 = 32 bytes b00101 = 64 bytes b00110 = 128 bytes b00111 = 256 bytes b01000 = 512 bytes b01001 = 1KB b01010 = 2KB b01011 = 4KB | b01100 = 8KB b01101 = 16KB b01110 = 32KB b01111 = 64KB b10000 = 128KB b10001 = 256KB b10010 = 512KB b10011 = 1MB b10100 = 2MB b10101 = 4MB | b10110 = 8MB b10111 = 16MB b11000 = 32MB b11001 = 64MB b11010 = 128MB b11011 = 256MB b11100 = 512MB b11101 = 1GB b11110 = 2GB b11111 = 4GB. |
[0] | Enable | Enables or disables a memory region: 0 = Memory region disabled. Memory regions are disabled on reset. 1 = Memory region enabled. A memory region must be enabled before it is used. | ||
[a] Sub-region 0 covers the least significant addresses in the region, while sub-region 7 covers the most significant addresses in the region. For more information, see Subregions. | ||||
To access an MPU Region Size and Enable Register, read or write CP15 with:
MRC p15, 0, <Rd>, c6, c1, 2 ; Read Data MPU Region Size and Enable Register MCR p15, 0, <Rd>, c6, c1, 2 ; Write Data MPU Region Size and Enable Register
Writing a region size that is outside the range results in Unpredictable behavior.
The MPU Region Access Control Register characteristics are:
Holds the region attributes and access permissions for the region specified by the Memory Region Number Register.
The MPU Region Access Control Registers are:
read/write registers
accessible in Privileged mode only.
Use these registers if the processor is configured with an MPU.
See Table 4.35.
Figure 4.36 shows the MPU Region Access Control Registers bit assignments.
Table 4.35 shows the MPU Region Access Control Registers bit assignments.
Table 4.35. MPU Region Access Control Register bit assignments
Bits | Name | Function |
|---|---|---|
[31:13] | - | SBZ. |
| [12] | XN | Execute Never. Determines if a region of memory is executable: 0 = all instruction fetches enabled 1 = no instruction fetches enabled. |
| [11] | - | Reserved. |
| [10:8] | AP | Access permission. Defines the data access permissions. For more information on AP bit values, see Table 4.38. |
| [7:6] | - | SBZ. |
| [5:3] | TEX | Type extension. Defines the type extension attribute[a]. |
| [2] | S | Share. Determines if the memory region is Shared or Non-shared: 0 = Non-shared. 1 = Shared. This bit only applies to Normal, not Device or Strongly Ordered memory. |
| [1] | C | C bit[a]: |
| [0] | B | B bit[a]: |
[a] For more information on this region attribute, see Table 4.36. | ||
Table 4.36 shows the encoding for the TEX[2:0], C, and B regions.
Table 4.36. TEX[2:0], C, and B encodings
| TEX[2:0] | C | B | Description | Memory Type | Shareable? | |
|---|---|---|---|---|---|---|
| 000 | 0 | 0 | Strongly-ordered. | Strongly-ordered | Shareable | |
| 000 | 0 | 1 | Shareable Device. | Device | Shareable | |
| 000 | 1 | 0 | Outer and Inner write-through, no write-allocate. | Normal | S bit[a] | |
| 000 | 1 | 1 | Outer and Inner write-back, no write-allocate. | Normal | S bit[a] | |
| 001 | 0 | 0 | Outer and Inner Non-cacheable. | Normal | S bit[a] | |
| 001 | 0 | 1 | Reserved. | - | - | |
| 001 | 1 | 0 | ||||
| 001 | 1 | 1 | Outer and Inner write-back, write-allocate. | Normal | S bit[a] | |
| 010 | 0 | 0 | Non-shareable Device. | Device | Non-shareable | |
| 010 | 0 | 1 | Reserved. | - | - | |
| 010 | 1 | X | Reserved. | - | - | |
| 011 | X | X | Reserved. | - | - | |
| 1BB | A | A | Cacheable memory: | AA[b] = Inner policy BB[b] = Outer policy | Normal | S bit[a] |
[a] Region is Shareable if S == 1, and Non-shareable if S == 0. [b] Table 4.37 shows the encoding for these bits. | ||||||
When TEX[2] == 1, the memory region is Cacheable memory, and the rest of the encoding defines the Inner and Outer cache policies:
defines the Outer cache policy
defines the Inner cache policy
The same encoding is used for the Outer and Inner cache policies. Table 4.37 shows the encoding.
Table 4.37. Inner and Outer cache policy encoding
| Memory attribute encoding | Cache policy |
|---|---|
| 00 | Non-cacheable |
| 01 | Write-back, write-allocate |
| 10 | Write-through, no write-allocate |
| 11 | Write-back, no write-allocate |
Table 4.38 shows the AP bit values that determine the permissions for Privileged and User data access.
Table 4.38. Access data permission bit encoding
| AP bit values | Privileged permissions | User permissions | Description |
|---|---|---|---|
| b000 | No access | No access | All accesses generate a permission fault |
| b001 | Read/write | No access | Privileged access only |
| b010 | Read/write | Read-only | Writes in User mode generate permission faults |
| b011 | Read/write | Read/write | Full access |
| b100 | UNP | UNP | Reserved |
| b101 | Read-only | No access | Privileged read-only |
| b110 | Read-only | Read-only | Privileged/User read-only |
| b111 | UNP | UNP | Reserved |
To access the MPU Region Access Control Registers read or write CP15 with:
MRC p15, 0, <Rd>, c6, c1, 4 ; Read MPU Region Access Control Register
MCR p15, 0, <Rd>, c6, c1, 4 ; Write MPU Region Access Control Register
To execute instructions in User and Privileged modes:
the region must have read access as defined by the AP bits
the XN bit must be set to 0.
The RGNRs characteristics are:
Multiple registers with one register for each memory region implemented. The value contained in the RGNR determines which of the multiple registers is accessed.
The RGNRs are:
Read/write register.
Accessible in Privileged mode only.
Writing this register with a value greater than or equal to the number of regions from the MPUIR is Unpredictable. Associated MPU Region Register accesses are also Unpredictable.
Use this register if the processor is configured with an MPU.
See Table 4.39.
Figure 4.37 shows the bit assignments.
Table 4.39 shows the bit assignments.
Table 4.39. RGNR bit assignments
Bits | Name | Function |
|---|---|---|
| [31:4] | - | SBZ. |
| [3:0] | Region | Defines the group of registers to be accessed. Read the MPUIR to determine the number of supported regions, see c0, MPU Type Register. |
To access the RGNR, read or write CP15 with:
MRC p15, 0, <Rd>, c6, c2, 0 ; Read RGNR
MCR p15, 0, <Rd>, c6, c2, 0 ; Write RGNR
| Copyright © 2010-2011 ARM. All rights reserved. | ARM DDI 0460C |
| Non-Confidential | ID021511 |
| PDF version | |
| Home > System Control > Register descriptions > c6, MPU memory region programming registers |