6.3.1. c9, Performance Monitor Control Register

The PMCR Register characteristics are:


Controls the operation of the three count registers, and the PMCCNTR Register.

Usage constraints

The PMCR Register is:

  • a read/write register

  • accessible in:


Available in all processor configurations.


Figure 6.1 shows the bit assignments.

Figure 6.1. PMCR Register bit assignments

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Table 6.2 shows the bit assignments.

Table 6.2. PMCR Register bit assignments



Implementer code:

0x41 = ARM


Identification code:

0x15 = Cortex-R5


Specifies the number of counters implemented:

0x3 = three counters implemented

[10: 6]ReservedRAZ on reads, Should Be Zero or Preserved (SBZP) on writes

Disable PMCCNTR when prohibited, that is, when non-invasive debug is not enabled:

0 = Count is enabled in prohibited regions. This is the reset value.

1 = Count is disabled in prohibited regions.


Enable export of the events to the event bus for an external monitoring block, for example the ETM, to trace events:

0 = Export disabled. This is the reset value.

1 = Export enabled.


Cycle count divider:

0 = Counts every processor clock cycle. This is the reset value.

1 = Counts every 64th processor clock cycle.


Cycle counter reset:

Write one to this bit to reset the cycle counter, PMCCNTR, to zero.

This bit Reads-As-Zero.


Event counter reset:

Write one to this bit to reset all event counters to zero.

This bit Reads-As-Zero.



0 = Disable all counters, including PMCCNTR. This is the reset value.

1 = Enable all counters including PMCCNTR.

The PMCR Register is always accessible in Privileged mode. To access the register, read or write CP15 with:

MRC p15, 0, <Rd>, c9, c12, 0 ; Read  PMCR Register
MCR p15, 0, <Rd>, c9, c12, 0 ; Write PMCR Register
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