13.3. Processor integration testing

This section describes the behavior and use of the Integration Test Registers that are in the processor. It also describes the Integration Mode Control Register that controls the use of the Integration Test Registers. For more information about the DBGITCTRL see the ARM Architecture Reference Manual.

If you want to utilise the integration test registers you must first set bit [0] of the Integration Mode Control Register to 1.

Various CoreSight components, including ETM-R5, also include Integration Test Registers that you can use in conjunction with processor Integration Test Registers for testing the connectivity between them. For more information see the relevant documentation, for example the ETM-R5 Technical Reference Manual

Table 13.2. Output signals that can be controlled by the Integration Test Registers

SignalRegisterBitRegister description
DBGRESTARTEDmDBGITMISCOUT[9]See DBGITMISCOUT Register (Miscellaneous Outputs)
DBGTRIGGERmDBGITMISCOUT[8]
ETMWFIPENDINGmDBGITMISCOUT[5]
nPMUIRQmDBGITMISCOUT[4]
COMMTXmDBGITMISCOUT[2]
COMMRXmDBGITMISCOUT[1]
DBGACKmDBGITMISCOUT[0]
EVNTBUSm[54, 0]DBGITETMIF[13:12]See DBGITETMIF Register (ETM interface)
ETMCIDm[31, 0]DBGITETMIF[11:10] 
ETMDAm[31, 0]DBGITETMIF[7:6] 
ETMDCTLm[11, 0]DBGITETMIF[5:4] 
ETMDDm[63, 0]DBGITETMIF[9:8] 
ETMIAm[31, 1]DBGITETMIF[3:2] 
ETMICTLm[13, 0]DBGITETMIF[1:0] 

Table 13.3. Input signals that can be read by the Integration Test Registers

SignalRegisterBitRegister description
DBGRESTARTmDBGITMISCIN[11]See DBGITMISCIN Register (Miscellaneous Inputs)
ETMEXTOUTm[1:0]DBGITMISCIN[9:8]
nETMWFIREADYmDBGITMISCIN[5]
nIRQmDBGITMISCIN[2]
nFIQmDBGITMISCIN[1]
EDBGRQmDBGITMISCIN[0]

This section describes:

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