4.3.22. Cache operations

The purpose of c7 is to manage the associated caches. The maintenance operations are formed into two management groups:

In addition, the maintenance operations use these definitions:

Point of Coherency (PoC)

A point where all instruction and data walks are transparent to any processor in the system.

Point of Unification (PoU)

A point where instruction and data become unified and self-modifying code can function.

Figure 4.38 shows the arrangement of the functions in this group that operate with the MCR and MRC instructions.

Note

The following operations, as Figure 4.38 shows, are implemented as No Operation, NOP, on the processor:

  • Wait For Interrupt, CRm = c0, Opcode_2 = 4

  • Invalidate all branch predictors Inner Shareable, CRm = c1, Opcode_2 = 6

  • Invalidate Entire Branch Predictor Array, CRm = c5, Opcode_2 = 6

  • Invalidate Branch Predictor Array Line using MVA, CRm = c5, Opcode_2 = 7

The Wait For Interrupt (WFI) instruction provides the Wait For Interrupt function. For more information see the ARM Architecture Reference Manual.

Figure 4.38. Cache operations

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In addition to the register c7 cache management functions in this processor, an Invalidate all data caches operation is provided as a c15 operation. For convenience, this c15 operation is also described in this section.

Note

  • Writing c7 with a combination of CRm and Opcode_2 not listed in Figure 4.38 results in an Undefined Instruction exception.

  • In this processor, reading from c7 causes an Undefined Instruction exception.

  • All accesses to c7 can only be executed in a Privileged mode of operation, except for the Instruction Synchronization Barrier, Data Synchronization Barrier, and Data Memory Barrier operations. These can be performed in User mode. Attempting to execute a Privileged instruction in User mode results in an Undefined Instruction exception.

  • This processor does not contain an address-based branch predictor array.

Invalidate and clean operations

The terms that describe the invalidate, clean, and prefetch operations are defined in the ARM Architecture Reference Manual.

You can perform invalidate and clean operations on:

  • single cache lines

  • entire caches.

Set and Way format

Figure 4.39 shows the Set and Way bit assignments.

Figure 4.39. c7 Set and Way bit assignments

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Table 4.40 shows the Set and Way bit assignments.

Table 4.40. c7 Set and Way bit assignments

Bits

Name

Function

[31:30]

Way

Indicates the cache way to invalidate or clean.
[29:S+5]-SBZ.
[S+4:5]SetIndicates the cache set to invalidate or clean. Because the cache sizes are configurable, the width of the Set field is unique to the cache size. See Table 4.41.
[4:0]-SBZ.

Table 4.41 shows the cache sizes and the resultant bit range for Set.

Table 4.41. Widths of the set field for L1 cache sizes

SizeSet
4KB[9:5]
8KB[10:5]
16KB[11:5]
32KB[12:5]
64KB[13:5]

See c0, Cache Type Register for more information on cache sizes.

Address format

Figure 4.40 shows the invalidate and clean operations bit assignments.

Figure 4.40. Invalidate and clean operations bit assignments

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Table 4.42 shows the invalidate and clean operations bit assignments.

Table 4.42. Invalidate and clean operations bit assignments

Bits

Name

Function

[31:5]

Address

Specifies the address to invalidate or clean

[4:0]ReservedSBZ

Data Synchronization Barrier operation

The purpose of the Data Synchronization Barrier operation is to ensure that all outstanding explicit memory transactions complete before any following instructions begin. This ensures that data in memory is up to date before the processor executes any more instructions.

The Data Synchronization Barrier Register is:

  • a write-only operation

  • accessible in both User and Privileged mode.

To access the Data Synchronization Barrier operation, write CP15 with:

MCR p15, 0, <Rd>, c7, c10, 4 ; Data Synchronization Barrier operation

For more information about memory barriers, see the ARM Architecture Reference Manual.

Data Memory Barrier operation

The purpose of the Data Memory Barrier operation is to ensure that all outstanding explicit memory transactions complete before any following explicit memory transactions begin. This ensures that data in memory is up to date before any memory transaction that depends on it.

The Data Memory Barrier operation is:

  • write-only

  • accessible in User and Privileged mode.

To access the Data Memory Barrier operation write CP15 with:

MCR p15, 0, <Rd>, c7, c10,5  ; Data Memory Barrier Operation

For more information about memory barriers, see the ARM Architecture Reference Manual.

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