6.3.3. c9, Count Enable Clear Register

The PMCNTENCLR Register characteristics are:

Purpose

Disables any of the Event Count Registers.

Usage constraints

The PMCNTENCLR Register is:

Configurations

Available in all processor configurations.

Attributes

Figure 6.3 shows the bit assignments.

Figure 6.3. PMCNTENCLR Register bit assignments

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Table 6.4 shows the bit assignments.

Table 6.4. PMCNTENCLR Register bit assignments

BitsNameFunction

[31]

C

Cycle counter disable:

[30:3]

Reserved

UNP on reads, SBZP on writes

[2]

P2

Counter 2 enable

[1]

P1

Counter 1 enable

[0]

P0

Counter 0 enable


To access the PMCNTENCLR Register, read or write CP15 with:

MRC p15, 0, <Rd>, c9, c12, 2 ; Read  PMCNTENCLR Register
MCR p15, 0, <Rd>, c9, c12, 2 ; Write PMCNTENCLR Register

When reading this register, any enable that reads as 0 indicates the corresponding counter is disabled. Any enable that reads as 1 indicates the corresponding counter is enabled.

When writing this register, any enable written with a value of 0 is ignored, that is, not updated. Any enable written with a value of 1 clears the counter enable. You must use the Count Enable Set Register to enable the counters. All counters are disabled at reset.

Writing to bits in this register disables individual counters, and clears the corresponding bits in the PMCNTENSET Register, see c9, Count Enable Set Register.

You can use the enable, EN, bit [0] of the PMCR Register to disable all performance counters including PMCCNTR, see c9, Performance Monitor Control Register.

The PMCNTENCLR and PMCNTENSET Registers retain their values when the enable bit of the PMCR is clear, even though their settings are ignored. The PMCNTENCLR Register can be used to clear the enabled flags for individual counters even when all counters are disabled in the PMCR Register.

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