6.3.2. c9, Count Enable Set Register

The PMCNTENSET Register characteristics are:


Enables the Event Count Registers.

Usage constraints

The PMCNTENSET Register is:


Available in all processor configurations.


Figure 6.2 shows the bit assignments.

Figure 6.2. PMCNTENSET Register bit assignments

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Table 6.3 shows the bit assignments.

Table 6.3. PMCNTENSET Register bit assignments




Cycle counter enable



UNP on reads, SBZP on writes



Counter 2 enable



Counter 1 enable



Counter 0 enable

To access the PMCNTENSET Register, read or write CP15 with:

MRC p15, 0, <Rd>, c9, c12, 1 ; Read PMCNTENSET Register
MCR p15, 0, <Rd>, c9, c12, 1 ; Write PMCNTENSET Register

When reading this register, any enable that reads as 0 indicates the corresponding counter is disabled. Any enable that reads as 1 indicates the corresponding counter is enabled.

Writing a 1 to a particular count enable bit enables that counter. Writing a 0 to a count enable bit has no effect. You must use the Count Enable Clear Register to disable the counters. All counters are disabled at reset.

The PMCNTENSET Register retains its value when the enable bit of the PMCR is clear, even though its settings are ignored.

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