4.3.11. Instruction Set Attributes Registers

There are eight Instruction Set Attributes Registers, ID_ISAR0 to ID_ISAR7, but three of these are unused. This section describes:

c0, Instruction Set Attributes Register 0

The ID_ISAR0 characteristics are:

Purpose

Provides information about the instruction set that the processor supports, beyond the basic set.

Usage constraints

The ID_ISAR0 is:

  • a read-only register

  • accessible in Privileged mode only.

Configurations

Available in all processor configurations.

Attributes

Figure 4.19 shows the ID_ISAR0 bit assignments.

Figure 4.19. ID_ISAR0 bit assignments

To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.


Table 4.15 shows the ID_ISAR0 bit assignments.

Table 4.15. ID_ISAR0 bit assignments

Bits NameFunction
[31:28]-

SBZ

[27:24]Divide instructions

Indicates support for divide instructions.

0x1 = Support for UDIV and SDIV in the Thumb ISA. Applies to Cortex-R5, r0p0.

0x2 = Support for UDIV and SDIV in the ARM and Thumb ISA. Applies from Cortex-R5, r1p0.

[23:20]Debug instructions

Indicates support for debug instructions.

0x1 = the processor supports BKPT.

[19:16]Coprocessor instructions

Indicates support for coprocessor instructions other than separately attributed feature registers, such as CP15 registers and VFP.

0x0 = no support.

[15:12]Compare and branch instructions

Indicates support for combined compare and branch instructions.

0x1 = the processor supports combined compare and branch instructions, CBNZ and CBZ.

[11:8]Bitfield instructions

Indicates support for bitfield instructions.

0x1 = the processor supports bitfield instructions, BFC, BFI, SBFX, and UBFX.

[7:4]Bit counting instructions

Indicates support for bit counting instructions.

0x1 = the processor supports CLZ.

[3:0]Atomic instructions

Indicates support for atomic load and store instructions.

0x1 = the processor supports SWP and SWPB.


To access the ID_ISAR0, read CP15 with:

MRC p15, 0, <Rd>, c0, c2, 0 ; Read ID_ISAR0

c0, Instruction Set Attributes Register 1

The ID_ISAR1 characteristics are:

Purpose

Provides information about the instruction set that the processor supports beyond the basic set.

Usage constraints

The ID_ISAR1 is:

  • a read-only register

  • accessible in Privileged mode only.

Configurations

Available in all processor configurations.

Attributes

Figure 4.20 shows the ID_ISAR1 bit assignments.

Figure 4.20. ID_ISAR1 bit assignments

To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.


Table 4.16 shows the ID_ISAR1 bit assignments.

Table 4.16. ID_ISAR1 bit assignments

Bits Name Function
[31:28]Jazelle instructions

Indicates support for Jazelle instructions.

0x1 = the processor supports:

  • BXJ instruction

  • J bit in PSRs.

For more information see Program status registers and Acceleration of execution environments.

[27:24]Interworking instructions

Indicates support for interworking instructions.

0x3 = the processor supports:

  • BX, and T bit in PSRs

  • BLX, and PC loads have BX behavior.

  • Data-processing instructions in the ARM instruction set with the PC as the destination and the S bit clear have BX-like behavior.

[23:20]Immediate instructions

Indicates support for immediate instructions.

0x1 = the processor supports:

  • the MOVT instruction

  • MOV instruction encodings with 16-bit immediates

  • Thumb ADD and SUB instructions with 12-bit immediates.

[19:16]ITE instructions

Indicates support for if then instructions.

0x1 = the processor supports IT instructions.

[15:12]Extend instructions

Indicates support for sign or zero extend instructions.

0x2 = the processor supports:

  • SXTB, SXTB16, SXTH, UXTB, UXTB16, and UXTH

  • SXTAB, SXTAB16, SXTAH, UXTAB, UXTAB16, and UXTAH.

[11:8]Exception 2 instructions

Indicates support for exception 2 instructions.

0x1 = the processor supports RFE, SRS, and CPS.

[7:4]Exception 1 instructions

Indicates support for exception 1 instructions.

0x1 = the processor supports LDM (exception return), LDM (user registers), and STM (user registers).

[3:0]Endian instructions

Indicates support for endianness control instructions.

0x1 = the processor supports SETEND and E bit in PSRs.


To access the ID_ISAR1 read CP15 with:

MRC p15, 0, <Rd>, c0, c2, 1 ; Read ID_ISAR1

c0, Instruction Set Attributes Register 2

The ID_ISAR2 is:

  • a read-only register

  • accessible in Privileged mode only.

The ID_ISAR2 characteristics are:

Purpose

The ID_ISAR2 provides information about the instruction set that the processor supports beyond the basic set.

Usage constraints

The ID_ISAR2 is:

  • a read-only register

  • accessible in Privileged mode only.

Configurations

Available in all processor configurations.

Attributes

Figure 4.21 shows the ID_ISAR2 bit assignments.

Figure 4.21. ID_ISAR2 bit assignments

To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.


Table 4.17 shows the ID_ISAR2 bit assignments.

Table 4.17. ID_ISAR2 bit assignments

Bits

NameFunction
[31:28]Reversal instructions

Indicates support for reversal instructions.

0x2 = the processor supports REV, REV16, REVSH, and RBIT.

[27:24]PSR instructions

Indicates support for PSR instructions.

0x1 = the processor supports MRS and MSR, and the exception return forms of data-processing instructions.

[23:20]Unsigned multiply instructions

Indicates support for advanced unsigned multiply instructions.

0x2 = the processor supports:

  • UMULL and UMLAL

  • UMAAL.

[19:16]Signed multiply instructions

Indicates support for advanced signed multiply instructions.

0x3 = the processor supports:

  • SMULL and SMLAL

  • SMLABB, SMLABT, SMLALBB,SMLALBT, SMLALTB, SMLALTT, SMLATB, SMLATT, SMLAWB, SMLAWT, SMULBB, SMULBT, SMULTB, SMULTT, SMULWB, SMULWT, and Q flag in PSRs

  • SMLAD, SMLADX, SMLALD, SMLALDX, SMLSD, SMLSDX, SMLSLD, SMLSLDX, SMMLA, SMMLAR, SMMLS, SMMLSR, SMPUL, SMPULR, SMUAD, SMUADX, SMUSD, and SMUSDX.

[15:12]Multiply instructions

Indicates support for multiply instructions.

0x2 = the processor supports MUL, MLA, and MLS.

[11:8]Interruptible instructions

Indicates support for multi-access interruptible instructions.

0x1 = the processor supports restartable LDM and STM.

[7:4]Memory hint instructions

Indicates support for memory hint instructions.

0x3 = the processor supports PLD and PLI. Applies to Cortex-R5, r0p0

0x4 = the processor supports PLD, PLI and PLDW. Applies from Cortex-R5, r1p0

[3:0]Load/store instructions

Indicates support for additional load and store instructions.

0x1 = the processor supports LDRD and STRD.


To access the ID_ISAR2 read CP15 with:

MRC p15, 0, <Rd>, c0, c2, 2 ; Read ID_ISAR2

c0, Instruction Set Attributes Register 3

The ID_ISAR3 characteristics are:

Purpose

Provides information about the instruction set that the processor supports beyond the basic set.

Usage constraints

The ID_ISAR3 is:

  • a read-only registers

  • accessible in Privileged mode only.

Configurations

Available in all processor configurations.

Attributes

Figure 4.22 shows the ID_ISAR3 bit assignments.

Figure 4.22. ID_ISAR3 bit assignments

To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.


Table 4.18 shows the ID_ISAR3 bit assignments.

Table 4.18. ID_ISAR3 bit assignments

Bits

NameFunction
[31:28]ThumbEE extension

Indicates support for ThumbEE Execution Environment extension.

0x0 = no support.

[27:24]True NOP instructions

Indicates support for true NOP instructions.

0x1 = the processor supports NOP16, NOP32 and various NOP compatible hints in both the ARM and Thumb instruction sets.

[23:20]Thumb copy instructions

Indicates support for Thumb copy instructions.

0x1 = the processor supports Thumb MOV(3) low register ⇒ low register.

[19:16]Table branch instructions

Indicates support for table branch instructions.

0x1 = the processor supports table branch instructions, TBB and TBH.

[15:12]Synchronization primitive instructions

Indicates support for synchronization primitive instructions.

0x2 = the processor supports:

  • LDREX and STREX

  • LDREXB, LDREXH, LDREXD, STREXB, STREXH, STREXD, and CLREX.

[11:8]SVC instructions

Indicates support for SVC (formerly SWI) instructions.

0x1 = the processor supports SVC.

[7:4]SIMD instructions

Indicates support for Single Instruction Multiple Data (SIMD) instructions.

0x3 = the processor supports:

PKHBT, PKHTB, QADD16, QADD8, QASX, QSUB16, QSUB8, QSAX, SADD16, SADD8, SASX, SEL, SHADD16, SHADD8, SHASX, SHSUB16, SHSUB8, SHSAX, SSAT, SSAT16, SSUB16, SSUB8, SSAX, SXTAB16, SXTB16, UADD16, UADD8, UASX, UHADD16, UHADD8, UASX, UHSUB16, UHSUB8, USAX, UQADD16, UQADD8, UQASX, UQSUB16, UQSUB8, UQSAX, USAD8, USADA8, USAT, USAT16, USUB16, USUB8, USAX, UXTAB16, UXTB16, and the GE[3:0] bits in the PSRs.

[3:0]Saturate instructions

Indicates support for saturate instructions.

0x1 = the processor supports QADD, QDADD, QDSUB, QSUB and Q flag in PSRs.


To access the ID_ISAR3 read CP15 with:

MRC p15, 0, <Rd>, c0, c2, 3 ; Read ID_ISAR3

c0, Instruction Set Attributes Register 4

The ID_ISAR4 characteristics are:

Purpose

Provides information about the instruction set that the processor supports beyond the basic set.

Usage constraints

The ID_ISAR4 is:

  • a read-only register

  • accessible in Privileged mode only.

Configurations

Available in all processor configurations.

Attributes

Figure 4.23 shows the ID_ISAR4 bit assignments.

Figure 4.23. ID_ISAR4 bit assignments

To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.


Table 4.19 shows the ID_ISAR4 bit assignments.

Table 4.19. ID_ISAR4 bit assignments

Bits

NameFunction
[31:28]SWP_fracRAZ because SWP/SWPB instruction support is indicated in ID_ISAR0.
[27:24]PSR_M_instrs

Indicates support for M-profile instructions for modifying the PSRs.

0x0 = no support.

[23:20]Exclusive instructions

Indicates support for Exclusive instructions.

0x0 = Only supports synchronization primitive instructions as indicated by bits [15:12] in the ISAR3 register. See c0, Instruction Set Attributes Register 3 for more information.

[19:16]Barrier instructions

Indicates support for Barrier instructions.

0x1 = the processor supports DMB, DSB, and ISB instructions.

[15:12]SMC instructions

Indicates support for Secure Monitor Call (SMC) (formerly SMI) instructions.

0x0 = no support.

[11:8]Write-back instructions

Indicates support for write-back instructions.

0x1 = supports all the writeback addressing modes defined in ARMv7.

[7:4]With shift instructions

Indicates support for with-shift instructions.

0x4 = the processor supports:

  • the full range of constant shift options, on load/store and other instructions

  • register-controlled shift options.

[3:0]Unprivileged instructions

Indicates support for Unprivileged instructions.

0x2 = the processor supports LDR{SB|B|SH|H}T and STR{B|H}T.


To access the ID_ISAR4 read CP15 with:

MRC p15, 0, <Rd>, c0, c2, 4 ; Read ID_ISAR4

c0, Instruction Set Attributes Register 5

The ID_ISAR5 characteristics are:

Purpose

Provides additional information about the properties of the processor.

Usage constraints

ID_ISAR5 is:

  • a read-only register

  • accessible in Privileged mode only.

Configurations

Available in all processor configurations.

Attributes

In the processor, ID_ISAR5 is read as 0x00000000.

To access the ID_ISAR5, read CP15 with:

MRC p15, 0, <Rd>, c0, c2, 5 ; Read Instruction Set Attribute Register 5

c0, Instruction Set Attributes Registers 6-7

ID_ISAR6 and ID_ISAR7 are not implemented, and their positions in the register map are Reserved. They correspond to CP15 accesses with:

MRC p15, 0, <Rd>, c0, c2, 6 ; Read ID_ISAR6
MRC p15, 0, <Rd>, c0, c2, 7 ; Read ID_ISAR7

These registers are read-only, and are accessible in Privileged mode only.

Copyright © 2010-2011 ARM. All rights reserved.ARM DDI 0460C
Non-ConfidentialID021511